The Vivado Design Suite from Xilinx is used for the synthesis and analysis of HDL designs for Xilinx FPGAs, superseding the Xilinx ISE Design Suite with additional features for SoC development and high-level synthesis. This tool increases the overall productivity for designing, integrating and implementing systems with Xilinx’s UltraScale, 7 series devices, and Zynq-7000. In this article, we’ll be using the Vivado IP Integrator alongside the Vivado SDK to create the classic “Hello World” project for the Proteus Kintex 7 FPGA development board containing a 32-bit MicroBlaze soft processor and peripherals connected together by the AXI4 bus.
What is Microblaze?
MicroBlaze is a 32-bit soft processor IP developed by Xilinx for their mid and high-end FPGA devices. It is compatible with Xilinx’s 6 and 7 series FPGAs. More information on Microblaze can be found at Xilinx’s MicroBlaze page. Advanced knowledge of MicroBlaze or AXI is not a prerequisite to follow this article. Thanks to the excellent tools provided by Xilinx, most of the design can be done without writing any code at all.
What is AXI?
AXI stands for Advanced eXtensible Interface. AXI is an interconnected bus based on ARM’s popular AMBA bus architecture. In a Microblaze system, the AXI connects the microprocessor to all peripherals in the system. The only exception is the Block RAM which is attached to the processor through the LMB (Local Memory Bus). AXI4-Lite is available for connecting low throughput peripherals to the system such as UART, GPIO, etc. AXI4-Lite uses fewer logic resources on FPGA compared to AXI. Usually, AXI is used to connect high throughput peripherals such as DDR memory, Ethernet, etc. Again, a detailed understanding of AXI is not required for following this article. But for the curious readers, AXI Reference Guide is available here.
- Proteus Kintex 7 USB 3.1 FPGA Development Board
- Xilinx Platform Cable USB II JTAG debugger
- USB 3.0 A to Micro-B SuperSpeed cable
- Vivado Design Suite with SDK installed (>= 2018.2)
Creating Microblaze based Hardware Platform for Proteus
The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with a Microblaze soft processor using the Vivado IP integrator. Numato Lab’s Proteus Kintex 7 USB 3.1 FPGA Development Board is used in this example, but any compatible FPGA platform can be used with minor changes to the steps. Screenshots are added wherever possible to make the process easier for the reader.
Open the Xilinx Vivado Design suite, go to “File -> Project -> New” to create a new project. The “New project” window will pop up. Click “Next” to continue
In the “Project Name” window, type a name for the project (feel free to use any name) and select a convenient location to save the project. Select the checkbox below to keep all project files in a single folder and Click “Next” to proceed.
In the “Project type” window, select “RTL Project”, select the option “Do not specify sources at this time” and click “Next”.
At the “Default Part” window, select the “Boards” tab and select the vendor as “numato.com”. Select the board name “Proteus” and click “Next” to continue. If Proteus is not displayed in the “Boards” list, you will have to install the Proteus board support files correctly and retry this step. You can download the Proteus board support files for Vivado from here. Follow the “readme” in the link on how to install the Vivado board files in your system.
In the “Flow Navigator” panel, click “Create Block Design” under the IP integrator section. Give an appropriate name to the design and click “OK” (the author used “proteus_design” as the design name).
Step 6 :
We need to create a design using Microblaze IP along with other peripherals. The default peripherals available for the Proteus Board will be displayed in the “Board” section of the window as shown below in the screenshot.
Add System Clock and DDR3 SDRAM from the list of board peripherals to the design by double-clicking on the corresponding peripherals. In the design window, right-click and click “Add IP” in the popup menu. Search for ‘Microblaze’ and ‘AXI timer’ and add them to the design by double-clicking on them.
Double-click on the Clock IP block and configure it as shown below.
Remove the existing connection to ‘sys_clk_i’ and connect ‘clk_out2′ from the clocking Wizard to ‘sys_clk_i’ of the ‘MIG 7 Series’ block as shown in the image below.
Click “Run Block Automation” on the top left corner of the window to complete the design. Select the settings as shown in the image below. Click “OK” for Vivado to automatically configure the blocks for you. Once the Block Automation is complete, click “Run Connection Automation” so Vivado can connect the blocks together to make a complete system.
After clicking”Run Connection Automation”, you can see the complete design with all the IPs connected through the “AXI Interconnect”. Double-click on the MicroBlaze Debug Module (MDM) IP block to configure it. Select the “Enable JTAG UART” option as shown in the image below.
Connect interrupt output lines from “AXI Timer” and “MicroBlaze Debug Module” to the Concat block as shown in the picture below. The blocks in question are highlighted in red.
Right-click on the block design in the “Sources” window and click “Create HDL Wrapper” from the popup menu. Click “OK” in the window that appears to finish generating a wrapper.
Click “Generate Bitstream” under the “Program And Debug” section to synthesize, implement and generate the bitstream for the design.
Once the implementation and generation of the bitstream have been successfully completed, we need to export the hardware along with bitstream. Go to the “File” menu, select “Export -> Export Hardware”. Select “Include bitstream” and click “OK”
Launch SDK from the File menu. You may choose to use the local project directory as SDK workspace or select another directory. Once the SDK window appears, select “New -> Application Project” from the “File” menu. Enter a project name and click “Next” to select the “Hello World” template from the list of available templates.
Once the project is created, the SDK will automatically run a build. If that didn’t happen for any reason, run the build manually. Once the build is successfully completed, power up the Proteus Kintex 7 USB 3.1 FPGA Development Board using external DC power supply or the USB 3.0 Type-A to Micro-B SuperSpeed cable and connect the Xilinx Platform USB II JTAG cable to the board.
Program the FPGA on the Proteus board by going to “Program FPGA” under the “Xilinx” menu. Now run the application by clicking the Run icon in the main toolbar. Select “Launch on Hardware (System Debugger)” when asked as shown in the image below.
If everything went well, the HelloWorld application running on the board should print “Hello World” over the JTAG-UART which should be displayed in the SDK’s Console terminal as shown in the image below.