Mimas Artix 7 FPGA Development Board

Vivado Design Suite – Create Microblaze based design using IP Integrator With Mimas A7 FPGA development board

210 views September 4, 2018 vijayalakshmi 0

Introduction

Vivado Design Suite is developed by Xilinx and is used for the synthesis and analysis of HDL design with additional features for SOC development and high-level synthesis. Xilinx recommends use of Vivado Design Suite for new designs with Ultra scale, Virtex-7, Kintex-7, Artix-7, and Zynq-7000. Complete pack of Vivado Design Suite contains Vivado High-Level Synthesis, Vivado Simulator, Vivado IP Integrator and Vivado TCL Store. In this article, we will be using Vivado IP Integrator along with  Vivado SDK to create basic “Hello World” project for Mimas A7 FPGA Development Board. The design will contain a Microblaze soft processor and peripherals connected together by AXI bus. Thanks to the excellent tools provided by Xilinx, most of the design can be done without writing any code at all.

What is Microblaze?

Microblaze is a 32 bit soft processor IP developed by Xilinx for their mid – high end FPGA devices. Microblaze is compatible with Xilinx’s 6 and 7 series devices such as Spartan 6, Artix-7, Kintex-7, Virtex-7 and Zynq-7000 devices. More information and resources including datasheet for Microblaze can be found at Xilinx’s Microblaze page. Microblaze IP is bundled with Xilinx IP integrator. Microblaze based embedded design can use either PLB or AXI as the bus system. Since Xilinx is planning to phase out PLB and keep only AXI in the future, we will stick with AXI for our designs. Advanced knowledge of Microblaze or AXI is not a prerequisite to follow this article and build a working system successfully.

What is AXI?

AXI stands for Advanced eXtensible Interface. AXI is a bus interconnect based on ARM’s popular AMBA bus architecture. In a Microblaze system AXI connects the microprocessor to all peripherals in the system. The only exception is Block RAM which is attached to the processor through LMB (Local Memory Bus). AXILite is available for connecting low throughput peripherals to the system such as UART, GPIO etc.… AXILite uses less logic resources on FPGA compared to AXI. Usually AXI is used to connect high throughput peripherals such as DDR memory, Ethernet etc… Again, a detailed understanding of AXI is not required for following this article. But for the curious readers, AXI Reference Guide is available here.

Mimas A7 FPGA Development Board

Mimas A7 FPGA Development Board is the product in a series of Xilinx 7 Series FPGA based products. Mimas A7 offers built in USB interface that can be used to program the board as well as do debugging or data transfer with the host. With a XC7A50T FPGA on board, Mimas A7 is a great choice for learning, product development and OEM integration.

Prerequisites:

Hardware:
Software:
  • Vivado Design Suite with SDK installed.
  • FT_Prog tool for configuring on-board FT2232H USB Serial converter (download and install from FTDI website).

Creating Microblaze based Hardware Platform for Mimas A7

The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with Microblaze soft processor using IP integrator. Numato Lab’s Mimas Artix 7 FPGA Development Board is used in this example but any compatible FPGA platform can be used with minor changes to the steps. Screenshots are added wherever possible to make the process easier to the reader.

Step 1:

Open Vivado Design suite, go to “File->Project ->New” to create a new project. The “New project” window will pop up. Click “Next” to continue.

Step 2:

In the “Project Name” window, type in a name for the project and save it in a convenient location. For this example, “mimasa7_microblaze” is used as project name, but feel free to use any name. Select the check box below to keep all project files in a single folder. Click “Next” to proceed.

Step 3:

In the “Project type” window, select “RTL Project” and check the option “Do not specify sources at this time”. Click “Next”.

Step 4:

At the “Default Part” window, in “Boards” select vendor as “numato.com” and select the board name “Mimas_A7_50T”. Click “Next” to continue. If Mimas_A7_50T is not displayed in the boards list, you need to install Mimas A7 board support files appropriately and retry this step. You can download Mimas A7 board support files for Vivado from here. Follow the readme in the link on how to install the Vivado board files in your system.

 

In the next window, click “Finish” to create a new project. When the new project wizard exits, a new project will open up in Vivado with the selected settings.

Step 5:

In the “Flow Navigator” panel, select the “Create Block Design” under IP integrator section. Give the appropriate name to the design and click “OK” (author used “mimasa7_design” as design name). Select “Boards” in the “Block Design” block. The default peripherals available for the Mimas A7 Board will be displayed.

Step 6:

Add System Clock, DDR3 SDRAM and USB UART to the design by double clicking on the corresponding peripherals. In the design window, right click and select “Add IP” from the popup menu. Search for ‘Microblaze’ and ‘AXI timer’ and add them to the design by double clicking on them.

Step 7:

Double click on the Clock IP and make changes as shown below.

Step 8

Remove existing connection to ‘sys_clk_i’ and connect clk_out2′ net on the clocking Wizard to ‘sys_clk_i’ of ‘MIG 7 Series’ block as shown in the image below.

Step 9:

Click on “Run Block Automation” on the top left corner of the window to complete the design. Select the settings as shown in below image. Click “OK” for Vivado to automatically configure the blocks for you. Once Block Automation is complete, run “Connection Automation” so Vivado can connect the blocks together to make a complete system.

Step 10:

Connect interrupt output lines from AXI Timer and UARTLite to the Concat block as shown in the picture below. The blocks in question are highlighted in red.

Step 11:

Right click on the design in the “Sources” window, select “Create HDL Wrapper” from the popup menu. Click “OK” on the window that appears to finish generating wrapper.

Step 12:

Now, double click on “Generate Bitsteam” under “PROGRAM AND DEBUG” section to synthesis, implement and to generate bitstream.

Step 13:

Now, implemention and generation of bitstream is successfully completed. We need to export the hardware along with bitstream. Go to “File” menu, select “Export->Export Hardware”. Select “Include bitstream” and click “OK”

Step 14:

Launch SDK from File menu. You may choose to use the local project directory as SDK workspace or select another directory if appropriate. Once SDK window appears, select “New->Application Project” from the “File” menu. Type in a project name and click “Next” to select “Hello World” template from the list of available templates.

Step 15:

Once the project is created, SDK will automatically run a build. If that didn’t happen for any reason, run a build manually. Once the build is complete successfully, power up Mimas A7 FPGA Development Board and connect Xilinx Platform USB cable and USB Type B cable for Serial debugging to the board.

Step 16:

Program the board by selecting “Program FPGA” under “Xilinx Tools” menu. Open the serial port corresponding to Mimas A7 on your operating system using your preferred Serial Terminal software such as HyperTerminal, PuTTY, Tera Term etc.. Now run the application by clicking on the Run icon on the main toolbar. Select “Launch On Hardware (GDB)” when asked as shown in image below.

Open any serial terminal and connect to the COM Port corresponding to Mimas A7 board. If everything went well, the application running on the board should print “Hello World” over the USB UART and should be displayed on the Serial Terminal application.

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