Mimas Artix 7 FPGA Development Board

Vivado Design Suite – Create MicroBlaze based design using IP Integrator and Vitis with Mimas A7 FPGA development board

196 views April 1, 2022 gayathri-ks 0

Introduction

In this article, we will be using Vivado IP Integrator along with Vitis to create a basic “Hello World” project for Mimas A7 FPGA Development Board. The design will contain a Microblaze soft processor and peripherals connected by an AXI bus. MicroBlaze-based embedded design can use either PLB or AXI as the bus system. More information and resources including a datasheet for MicroBlaze can be found on Xilinx’s MicroBlaze page.

Mimas A7 FPGA Development Board

Mimas A7 FPGA Development Board is the product in a series of Xilinx 7 Series FPGA-based products. Mimas A7 offers a built-in USB interface that can be used to program the board as well as do debugging or data transfer with the host. With an XC7A50T FPGA on board, Mimas A7 is a great choice for learning, product development and OEM integration.

Mimas A7 (Artix-7) FPGA Dev Board

Prerequisites:

Hardware:
Software:
  • Vivado Design Suiteand Vitis HSL.
  • FT_Prog tool for configuring on-board FT2232H USB Serial converter (download and install from FTDI website).

 

Creating Microblaze based Hardware Platform for Mimas A7

The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with MicroBlaze soft processor using an IP integrator. Numato Lab’s Mimas Artix 7 FPGA Development Board is used in this example, but any compatible FPGA platform can be used with minor changes to the steps. Screenshots are added wherever possible to make the process easier for the reader.

Step 1:

Download and install Vivado Board Support Package files for Mimas A7 from here.

Step 2:

Launch Vivado Design Suite, go to “File->Project->New” to create a new project. The “New project” wizard will pop up. Click “Next” to continue.

Step 3:

Enter a name for the project and save it at a suitable location. Check the option “Create project subdirectory”. Click Next to continue.

Step 4:

In the Project Type window, select RTL Project and check the option “Do not specify sources at this time”. Click Next.

Step 5:

In the Default Part window, select “Mimas_A7_50T” from the Boards option. If Mimas_A7_50T is not listed, make sure board support files are installed correctly. Click Next to continue.

Click Finish to complete creating a new project. A new project will be created by Vivado with the selected settings.

Step 6:

In the Flow Navigator panel, select Create Block Design under IP INTEGRATOR. Enter a name for the block design and click OK. An empty block design will be created.

Step 7:

Click the Board tab. The default peripherals available for the Mimas A7 board will be displayed.

Step 8:

Add System Clock, DDR3 SDRAM and USB UART to the design by double-clicking the corresponding peripherals. In the Diagram window, right-click and select “Add IP” from the popup menu. Search for “MicroBlaze” & “AXI Timer” and add them to the design by double-clicking them.

Step 9:

Double click “Clocking Wizard” IP and customize “Output Clocks” settings as shown in the following image.

Step 10:

Remove existing ‘sys_clk_i’ connection and input port (if any) and connect ‘clk_out2‘ net on the clocking Wizard to ‘sys_clk_i’ of the ‘MIG 7 Series’ block as shown in the following image.

Step 11:

Click “Run Block Automation” present in the “Designer Assistance available” bar on the top left corner of the window to complete the design. Select the settings as shown in the following image. Click “OK” for Vivado to automatically configure the blocks for you. Once Block Automation is complete, run “Connection Automation” so Vivado can connect the blocks to make a complete system.

 

Step 12:

Connect interrupt output lines from “AXI Timer” and “UARTLite” to the “Concat” block as shown below figure. Select the “Validate Design” option from the Tools menu to make sure that connections are correct.

Step 13:

Right-click “mimas_a7” in the “Sources” window, and select “Create HDL Wrapper” from the popup menu. Click “OK” on the window that appears to finish generating a wrapper.

 

Step 14:

Click “Generate Bitstream” under the “Program And Debug” section to synthesize, implement and generate a bitstream.

Step 15:

After generating the bitstream successfully, select Export -> Export Hardware from the File menu. Click Next.

Select the “include bitstream” checkbox and click Next.

Provide the XSA file name and save it at a suitable location. Click Next and click Finish in the next dialog box.

 

Step 16:

Select Launch Vitis IDE from the Tools menu. Provide a Workspace directory and click Launch.

Step 17:

In Vitis, IDE window select Create Application Project and click Next in the dialog box that appears.

In the Platform window, select Create a new platform from hardware tab and import the XSA file which is already created (Provide XSA file location). Click Next.

Step 18:

In the Application Project Details window, give an appropriate name for the Vitis Project and click Next. Click Next in the Domain window.

Select the Hello World template from the list of available templates and click Finish.

Step 19:

Build the project. Once the build is completed successfully, power up Mimas A7 FPGA Development Board using an external DC power supply and connect the Xilinx Platform USB cable to the board.

Step 20:

Program the FPGA on Mimas A7 with a simple boot loop program by selecting the Program FPGA option from the Xilinx menu.

 

Step 21:

Open the COM port corresponding to Mimas A7 in any serial terminal (PuTTY, Tera Term, etc.) with a 9600 baud rate (the default baud rate given in UART IP).  Now, right-click on the .elf file in Project Explorer and select “Launch Hardware” as shown below.

 

If everything went well, the application running on the board should print “Hello World” over the USB UART and should be displayed on the Serial Terminal application.

 

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