Outputting Single Ended Clock Signals via GPIO Header – Neso Artix 7 FPGA Module

Introduction:

This article provides a comprehensive guide on transmitting multiple Megahertz Frequency Clock signals through the GPIO headers of the Neso Artix 7 FPGA module. Within this article, we will explore the procedure of generating 50MHz and 100MHz frequency signals and outputting them through the GPIO header. A step-by-step guide utilizing the Neso Artix 7 FPGA module will be provided to ensure successful implementation.

Prerequisites:

Hardware:

Neso Artix 7 FPGA Board
Xilinx Platform Cable USB II JTAG debugger (optional)

Software:

Xilinx Vivado Suite 2022.1 or newer
Tenagra FPGA System Management Software

Let’s get started:

Below are the instructions to guide you through the procedure of generating 10MHz clock in Neso.

Step 1:

Download and install Vivado Board Support Package files for Neso Artix 7 from here.

Step 2:

Open Vivado Design Suite, go to File->Project->New. The New Project window will open. Click Next.

Enter a name for the project and save it at a suitable location. Check the option “Create project subdirectory”. Click Next to continue.

Step 3:

In the Project Type window, select RTL Project and check the “Do not specify sources at this time” option. Click Next.

Step 4:

In the Default Part window, select “Neso” from the Boards option. Click Next to continue.

Click Finish to complete creating a new project. Vivado will create a new project with the selected settings.

Step 5:

In the Sources tab, right-click on the Design Sources and select Add Sources. It will open a new Add Sources window

Step 6:

In the Add Source window, select Add or create design source and click Next.

And in the Design or Create Design Source, click on Create File. Select the File type as Verilog and give a suitable File name,

Proceed by clicking OK and then proceed to click Finish .

Step 7:

For generating 100MHz and 50MHz clock signals, go to “Flow Navigator” panel, click IP Catalog under the “PROJECT MANAGER” section. In the IP Catalog, search for Clocking Wizard IP and double click on it. The “Customize IP” window will open.

In Clocking Options tab, give Component Name as “clk_wiz_0” and primary clock port name as clk_in1.

In Output Clocks tab, Provide clk_out1 value as 100MHz and clk_out2 value as 50MHz. Click OK.

Step 8:

Once the customization is done, generate Output Product Window will pop-up. Click on Generate.

Step 9:

After generating the Output Product, copy paste the given code into the newly created Design Source,

module top (input clk, output clk_out1, output clk_out2);

    clk_wiz_0 instance_name
       (
       // Clock out ports
            .clk_out1(clk_out1), // output clk_out1
            .clk_out2(clk_out2), // output clk_out2
      // Clock in ports
            .clk_in1(clk)); 

endmodule

Step 10:

Click on the Run Synthesis option. Once the synthesis process completes successfully without any errors, proceed to click on the Run Implementation option.

After completing the implementation process, select the “Open Implementation Design” option. Within the design, go to the I/O Ports Tab and ensure accurate specification of the Package pin for both the input clock pin and the output clock pins.

Here is the generated constraint file provided for your reference.

set_property PACKAGE_PIN F4 [get_ports clk]
set_property PACKAGE_PIN E2 [get_ports clk_out1]
set_property IOSTANDARD LVCMOS25 [get_ports clk]
set_property IOSTANDARD LVCMOS25 [get_ports clk_out1]
set_property IOSTANDARD LVCMOS25 [get_ports clk_out2]
set_property PACKAGE_PIN D5 [get_ports clk_out2]

In this specific setup, the clk_out1 signal is routed to SRCC pin E2, while the clk_out2 signal is routed to SRCC pin D5.

Step 11:

Select Generate Bitstream after a successful Implementation. Once the Bitstream in generated program the board using the bit/bin file. (programming Neso Artix 7 board is available in User manual)

Step 12:

The obtained output for the reference is shown here:

Neso Artix 7 FPGA Module