Xilinx Artix 7 FPGA Boards

Neso - Artix 7 FPGA Development Board

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Introduction

Neso_1__17693.1448984412.1280.1280

Neso is an easy to use FPGA Development board featuring Artix 7 FPGA. It is specially designed for development and integration of FPGA based accelerated features to other designs. This development board features Xilinx XC7A100T FPGA with FTDI’s FT2232H Dual-Channel USB device. The high speed USB 2.0 interface provides fast and easy configuration download to the on-board SPI flash. No programmer or special down loader cable is needed to download the bit stream to the board.

Applications

  • Product Prototype Development
  • Accelerated computing integration
  • Development and testing of custom embedded processors
  • Signal Processing
  • Communication devices development
  • Educational tool for Schools and Universities

Board features

  • FPGA: XC7A100T in CSG324 package
  • DDR3: 2Gb DDR3 (MT41J128M16JT-125:K)
  • Flash memory: 128 Mb SPI flash memory (N25Q128A13ESE40E)
  • 100MHz CMOS oscillator
  • High Speed USB 2.0 interface for On-board flash programming.
    Revision V1: FT2232H Channel A is dedicated for SPI Flash /JTAG Programming. Channel B can be used for custom applications.
    Revision V2: FT2232H Channel B is dedicated for SPI Flash /JTAG Programming. Channel A can be used for custom applications.
  • On-board voltage regulators for single power rail operation
  • FPGA configuration via JTAG and USB
  • Maximum IOs for user defined purposes FPGA – 140 IOs FT2232H – 8 IOs

 

How to Use NESO Artix 7 FPGA Development Board

Components/Tools Required

Along with the module, you may need the items in the list below for easy and fast installation.

1. USB A to Micro B cable.
2. DC Power supply (Optional).

Connection Diagram

This diagram should be used as a reference only. For detailed information, see Neso schematics at the end of this document. Details of individual connectors are as below.

USB Interface

neso-usbinterfaceThe on board full speed USB controller helps a PC/Linux/Mac computer to communicate with this module. Use a USB A to Micro B cable to connect with a PC. By default the module is powered from USB so make sure not to overcrowd unpowered USB hubs (the picture on the right shows USB Micro connector).

Note: In the revision V1 of Neso, FT2232H Channel A is dedicated for SPI Flash /JTAG Programming. Channel B can be used for custom applications. The revision V2 of Neso ships with FT2232H Channel B dedicated for SPI Flash /JTAG Programming whereas Channel A can be used for custom applications.

DC Power Supply

neso-dcpowersupplyThis module uses +5V power supply to function properly. By default the board is configured to use +5V supply from USB. So an external +5V power is not required unless USB port is unable to supply enough current. In most cases USB ports are capable of providing enough current for the module. Current requirement for this board largely depends on your application. Please consult FPGA data sheet for more details on power requirements. If for any reason, an external 5V power supply needs to be used for the module, the Power select jumper should be configured properly before connecting the power supply. Please refer to the marking on the board for more details.

Power Select

The Power Select header K1 is used to configure the power source for the board. Connect pins 1 and 2 to use USB power and connect pins 2 and 3 to use the external DC power.

VADJ Supply

This board is equipped with a rotary switch (J3) for selecting bank 35 IO voltage level. It is possible to select 3 different voltage level for the bank ie, 1.8V, 2.5V and 3.3V as per the user requirement. Possible rotary switch positions and the resultant VADJ voltages are illustrated below:

JTAG Connector

JTAG connector provides access to FPGA’s JTAG pins. A XILINX platform cable can be used to for JTAG programming.

neso-jtagcon

JTAG/SPI Jumper Configuration on FT2232H Configuration Channel

The configuration channel of FT2232H in Neso can be connected to the SPI bus that connects the SPI Flash chip to the FPGA or to the JTAG pins of the FPGA. By connecting SPI bus to FT2232H, the SPI flash can be directly programmed to save the configuration permanently (non-volatile, until erased). This is the default configuration set when Neso is shipped. In the revision V1 of Neso, FT2232H Channel A is the configuration channel and is dedicated for SPI Flash /JTAG Programming. Channel B can be used for custom applications. The revision V2 of Neso ships with FT2232H Channel B is the configuration channel and is dedicated for SPI Flash /JTAG Programming whereas Channel A can be used for custom applications.

When FT2232H configuration channel is connected to SPI, Neso Configuration Downloader utility can be used to program the board. When FT2232H configuration channel is connected to FPGA JTAG, the JTAG signals can be accessed directly through FT2232H. Neso Configuration Downloader utility currently does not support programming FPGA SRAM through JTAG.

Please see the tables below for information about selecting SPI or JTAG for FT2232H configuration channel. SPI must be selected for Neso Configuration Downloader utility to work.

Header P10

Jumper Configuration for SPI Jumper Configuration for JTAG
1 - 2 2 - 4
5 - 6
3 - 5
7 - 8 8 - 10
11 - 12
9 - 11

Important: These jumper settings are only meant for accessing the JTAG signals via FT2232H through USB using programs such as xc3sprog.  If you are using external JTAG such as Xilinx Platform Cable USB II connected to the JTAG header, then please do not change these jumpers. They should be in the factory-shipped SPI configuration. If the jumpers are changed to JTAG mode, and an external JTAG is used, then the external JTAG will not work.

GPIOs

This device is equipped with a maximum 140 user IO pins that can be used for various custom applications. All user IOs are length matched and can be used as differential pairs.

Header P4

Pin No. On
The Header
Artix-7 (CSG324) Pin No.Pin No. On
The Header
Artix-7 (CSG324) Pin No.
1
GND 2 3V3
3
VCCIN 4 GND
5
A14 6 A13
7 D13 8 D12
9 A11 10 B11
11 F14 12 F13
13 B14 14 B13
15 A16 16 A15
17
A9 18 A10
19 B12 20 C12
21 A8 22 B8
23
C10 24 C11
25 B9 26 C9
27 B6
28 B7
29 C5 30 C6
31
A5 32 A6
33
C7 34 D8
35 D7 36
E7
37 D4 38 D5
39 - 40 -
41 -42-
43 D3 44
E3
45-46-
47 A3 48 A4
49 GND 50 GND
51 GND 52 GND
53-54-
55 B2 56 B3
57C1 58
C2
59 A1 60 B1
61
G1 62 H1
63 E1 64 F1
65-66-
67 D2
68 E2
69 K1 70 K2
71 J2 72 J3
73 B4 74
C4
75
E5 76 E6
77
G2 78 H2
79 F3 80 F5
81 G3 82 G4
83 H5 84 H6
85
H4 86 J4
87 F6 88 G6
89GND90GND
91GND92GND
933V3943V3
953V3963V3

Header P5

Pin No. On
The Header
Artix-7 (CSG324) Pin No.Pin No. On
The Header
Artix-7 (CSG324) Pin No.
1
ACBUS0* 2 ACBUS1
3
3V3 4 GND
5
ACBUS2 6 ACBUS3
7 B16 8 B17
9 ACBUS4 10 ACBUS5
11 D14 12 C14
13 ACBUS6 14 ACBUS7
15 C16 16 C17
17
H14
18 G14
19 D15 20 C15
21 E15 22 E16
23
E17 24 D17
25 F15 26 F16
27 J14 28
H15
29 H17 30 G17
31
H16 32 G16
33
K13
34 J13
35 L15 36
L16
37 L18 38 M18
39 R12
40 R13
41 K15
42 J15
43 M16
44
M17
45GND46GND
47 GND48 GND
49 GND 50 GND
51 GND 52 GND
53R18 54 T18
55 P15
56 R15
57N15 58
N16
59 N14
60 P14
61
P17 62 R17
63 N17 64 P18
65U16
66 V17
67 U17
68 U18
69 U14
70 V14
71 V15 72 V16
73 T14 74
T15
75
R16 76
T16
77
T9 78 T10
79 T13
80 U13
81 T11
82 U11
83 R10 84 R11
85
V10 86 V11
87 U12 88 V12
89INITB903V3
91PROGB923V3
93GND94GND
95GND96GND

FT2232H – Artix-7 (CSG324) FPGA Connection Details

FTDI Pin No.
Pin Function (245 FIFO) Artix-7 Pin No.
38 D0 A18
39 D1 B18
40 D2 D18
41 D3 E18
43 D4 F1
44 D5
G18
45
D6 J17
46
D7 J18
48
RXF# G13
52
TXE# K16
53
RD# D9
54 WR# M13
55
SIWUB D10

Driver Installation

Installing on Windows

This product requires Numato Lab drivers to be installed for proper functioning when used with Windows. The driver can be downloaded from http://productdata.numato.com/assets/downloads/driver/Driver.zip Windows users should download and run the WHQL Certified executable file that will prompt to install the Numato Lab drivers. When driver installation is complete, the module should appear in Neso Flash Config Tool as Neso Artix-7 FPGA Module (see the picture).

Older Revision:

Neso USB Vendor ID 0403
Neso USB Product ID 6010

Latest Revision:

Neso USB Vendor ID 2A19
Neso USB Product ID 1005

Note: In the revision V1 of Neso, FT2232H Channel A is dedicated for SPI Flash /JTAG Programming. Channel B can be used for custom applications. The revision V2 of Neso ships with FT2232H Channel B dedicated for SPI Flash /JTAG Programming whereas Channel A can be used for custom applications.

Generating Bit Stream for Neso

HDL design needs to be converted to bit stream before it can be programmed to FPGA. Neso at this time accepts only binary (.bin) bitstream created by XILINX ISE (http://www.xilinx.com/tools/webpack.htm). Once the HDL is synthesized, it is easy to create a binary bit stream out of it. Please follow the steps below to generate binary bit stream from your design using ISE Web Pack.

Step 1: Right click on the “Generate Programming File” option in “Processes” window.

neso-bitstreamstep1

Step 2: Select “Process Properties” from the pop up menu. In the dialog box, check “Create Binary Configuration File” Check box and click “Apply”.

neso-bitstreamstep2

Step 3: Click “OK” to close the dialog box. Right click on “Generate Programming File” option again and select “Run”. Now you will be able to find a “.bin” file in the project directory and that file can be used for Neso configuration.

Powering Up Neso

Neso is factory configured to be powered directly from USB port so make sure that you are using a USB port that can power the board properly. It is recommended to connect the board directly to the PC instead using a hub. It is practically very difficult to estimate the power consumption of the board, as it depends heavily on your design and the clock used. XILINX provides tools to estimate the power consumption. In any case if power from USB is not enough for your application, external supply can be applied to the board. Jumper PWRSEL should be set up properly (short pin 1-2) to use the board on external power. Neso requires three different voltages, a 3.3V, a 1.8V supplies and a 1.3V supply. Onboard regulators derive these voltages from the USB/Ext power supply.

Configuring Neso Artix-7 Module

The Neso Artix-7 module can be configured by two methods,

a) Using Artix-7 configuration tool through USB.
b) Using the Xilinx programming cable.

Configuring Neso Using Configuration Tool

Neso has an on-board FTDI FT2232 device which facilitates easy reprogramming of on-board SPI flash through USB interface. The FTDI receives bit stream from the host application and program it in to the SPI Flash and lets the FPGA boot from the flash. The Neso configuration application can be downloaded from www.numato.com for free.

Step 1: Open Neso Config Tool. Click “Scan for Devices” if “Neso Artix-7 FPGA Module” is not detected automatically.

neso-configtoolstep1

Step 2: Click on “Load Binary” Select the “.bin” file, then click on “Program Flash” button. Wait till “Programming Completed” appears on the screen.

neso-configtoolstep2

Configuring Neso Using JTAG

Neso Artix-7 module features an on-board JTAG connector which facilitates easy reprogramming of SRAM and on-board SPI flash through JTAG programmer like “XILINX Platform-cable usb”. Programming Neso using JTAG requires “XILINX ISE iMPACT” software which is bundled with XILINX ISE Design Suite. To program the SPI flash we need a “.mcs” file needs to be generated from the “.bit” file. Steps for generating “.mcs” file are as below. Programming FPGA SRAM does not require a “.mcs” file to be generated.

Generating “.mcs” file for Neso using ISE iMPACT

Step 1: Open ISE iMPACT. Click on “Create PROM file(PROM file formatter)”. In the dialog box, select “Configure Single FPGA” in storage device type. Then click on the green arrow on the right side.

neso-jtagstep1

Step 2: Select 128M in Storage Device (bits).Now click on “Add Storage Device”, then the green arrow on the right side.

neso-jtagstep2

Step 3: Set an output file name and the output file location (the “.mcs” file will be generated at this location which will be required later for programming the FPGA), then click OK twice, then select the “.bit” file we already generated then click Open and click NO when it prompts to add another device file.

neso-jtagstep3

Step 4: Double click on “Generate File”. A “Generate Succeeded” will be displayed as shown in the image below if the “.mcs” the file is generated successfully.

neso-jtagstep4

Programming FPGA Using VIVADO

Step 1: Run VIVADO and open Hardware Manager. Select Tools -> Auto Connect.

neso-vivadostep1

Step 2: Go to Tools, Select Add Configuration Memory Device, then the FPGA device.

neso-vivadostep2

Step 3: In the dialogue box that appears, select Micron, SPI, 128Mb in the Manufacturer, Type and Density section respectively and select n25q128-3.3v. Then click OK.

neso-vivadostep3

Step 4: Select the configuration file (.bin) and click OK button to program.

neso-vivadostep4

Wait until programming completes.

neso-vivadowait

Technical Specifications

Parameter *
Value Unit
Basic Specifications
Number of GPIOs
148(Max)
On-board oscillator frequency (FXO-HC536R)
100 MHz
DDR3 Capacity 2 Gb
SPI Flash Memory (N25Q128A13ESE40E) 128 Mb
Power supply voltage (USB or external) 5 – 6 V
FPGA Specifications
Internal supply voltage relative to GND –0.5 to 1.1 V
Auxiliary supply voltage relative to GND –0.5 to 2.0 V
Output drivers supply voltage relative to GND –0.5 to 3.6 V

Mechanical Dimensions

neso-dimensions

Neso GPIO Easy Reference

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