Xilinx Artix 7 FPGA Boards

Neso is an easy to use FPGA Development board featuring Artix 7 FPGA. It is specially designed for the development and integration of FPGA based accelerated features to other designs. This development board features Xilinx XC7A100T FPGA with FTDI’s FT2232H Dual-Channel USB device. The high-speed USB 2.0 interface provides fast and easy configuration download to the on-board SPI flash. No programmer or special downloader cable is needed to download the bitstream to the board.

Applications

• Product Prototype Development
• Accelerated computing integration
• Development and testing of custom embedded processors
• Signal Processing
• Communication devices development
• Educational tool for Schools and Universities

Board features

• FPGA: XC7A100T in CSG324 package
• DDR3: 2Gb DDR3 (MT41J128M16JT-125:K)
• Flash memory: 128 Mb SPI flash memory (N25Q128A13ESE40E)
• 100MHz CMOS oscillator
• High-Speed USB 2.0 interface for On-board flash programming.
  Revision V1: FT2232H Channel A is dedicated to SPI Flash /JTAG Programming. Channel B can be used for custom applications.
  Revision V2: FT2232H Channel B is dedicated to SPI Flash /JTAG Programming. Channel A can be used for custom applications.
• On-board voltage regulators for single power rail operation
• FPGA configuration via JTAG and USB
• Maximum IOs for user-defined purposes FPGA – 140 IOs FT2232H – 8 IOs

Along with the module, you may need the items in the list below for easy and fast installation.

1. USB A to Micro B cable.
2. DC Power supply (Optional).

This diagram should be used as a reference only. For detailed information, see Neso schematics at the end of this document. The details of individual connectors are as below.

The onboard full-speed USB controller helps a Windows/Linux/Mac computer to communicate with this module. Use a USB A to Micro B cable to connect with a PC. By default, the module is powered from USB so make sure not to overcrowd unpowered USB hubs (the picture on the right shows USB Micro connector).

Note: In the revision V1 of Neso, FT2232H Channel A is dedicated to SPI Flash /JTAG Programming. Channel B can be used for custom applications. The revision V2 of Neso ships with FT2232H Channel B dedicated for SPI Flash /JTAG Programming whereas Channel A can be used for custom applications.

This module uses a +5V power supply to function properly. By default, the board is configured to use the +5V supply from USB. So an external +5V power is not required unless the USB port is unable to supply enough current. In most cases, USB ports are capable of providing enough current for the module. The current requirement for this board largely depends on your application. Please consult the FPGA datasheet for more details on power requirements. If for any reason, an external 5V power supply needs to be used for the module, the Power select jumper should be configured properly before connecting the power supply. Please refer to the marking on the board for more details.

The Power Select header K1 is used to configure the power source for the board. Connect pins 1 and 2 to use USB power and connect pins 2 and 3 to use the external DC power.

This board is equipped with a rotary switch (J3) for selecting a bank 35 IO voltage level. It is possible to select 3 different voltage levels for the bank ie, 1.8V, 2.5V and 3.3V as per the user requirement. Possible rotary switch positions and the resultant VADJ voltages are illustrated below:

A JTAG connector provides access to FPGA’s JTAG pins. A Xilinx platform cable can be used for JTAG programming.

The configuration channel of FT2232H in Neso can be connected to the SPI bus that connects the SPI Flash chip to the FPGA or to the JTAG pins of the FPGA. By connecting SPI bus to FT2232H, the SPI flash can be directly programmed to save the configuration permanently (non-volatile, until erased). This is the default configuration set when Neso is shipped. In the revision V1 of Neso, FT2232H Channel A is the configuration channel and is dedicated to SPI Flash /JTAG Programming. Channel B can be used for custom applications. The revision V2 of Neso ships with FT2232H Channel B is the configuration channel and is dedicated to SPI Flash /JTAG Programming whereas Channel A can be used for custom applications.

When the FT2232H configuration channel is connected to SPI, Neso Configuration Downloader utility can be used to program the board. When the FT2232H configuration channel is connected to FPGA JTAG, the JTAG signals can be accessed directly through FT2232H. Neso Configuration Downloader utility currently does not support programming FPGA SRAM through JTAG.

Please see the tables below for information about selecting SPI or JTAG for the FT2232H configuration channel. SPI must be selected for Neso Configuration Downloader utility to work.

Header P10

Important: These jumper settings are only meant for accessing the JTAG signals via FT2232H through USB using programs such as xc3sprog.  If you are using external JTAG such as Xilinx Platform Cable USB II connected to the JTAG header, then please do not change these jumpers. They should be in the factory-shipped SPI configuration. If the jumpers are changed to JTAG mode, and an external JTAG is used, then the external JTAG will not work.

This device is equipped with a maximum of 140 user IO pins that can be used for various custom applications. All user IOs are length matched and can be used as differential pairs.

Neso Revision V1:

Header P4

Header P5

FT2232H – Artix-7 (CSG324) FPGA Connection Details

Neso Revision V2:

Header P4

In Neso Revision V1, GPIO 130 and GPIO 131 were connected to pin locations C15 and D15 respectively.

In Neso Revision V2, in pin locations, C15 and D15, FTDI OE and FTDI CLKOUT signals are connected respectively. And GPIO 130 is now connected to pin J5 in Bank 35 and GPIO 131 is connected to pin T8 in Bank 34.

Header P5

FT2232H – Artix-7 (CSG324) FPGA Connection Details

This product requires Numato Lab drivers to be installed for proper functioning when used with Windows. The driver can be downloaded from https://numato.com/wp-content/uploads/2019/01/Driver.zip. Windows users should download and run the WHQL Certified executable file that will prompt them to install the Numato Lab drivers.

Neso Revision V1:

Neso Revision V2:

Note: In the revision V1 of Neso, FT2232H Channel A is dedicated to SPI Flash /JTAG Programming. Channel B can be used for custom applications. The revision V2 of Neso ships with FT2232H Channel B dedicated for SPI Flash /JTAG Programming whereas Channel A can be used for custom applications.

The Linux ships with the drivers required for Neso. It should be enough to run the following two commands in the terminal:

>> sudo modprobe stdi_sio
>> echo 2a19 1005 > /sys/bus/usb-serial/drivers/ftdi_sio/new_id

Neso is factory configured to be powered directly from the USB port so make sure that you are using a USB port that can power the board properly. It is recommended to connect the board directly to the PC instead of using a hub. It is practically very difficult to estimate the power consumption of the board, as it depends heavily on your design and the clock used. Xilinx provides tools to estimate power consumption. In any case, if power from USB is not enough for your application, external supply can be applied to the board. Jumper PWRSEL should be set up properly (short pin 1-2) to use the board on external power. Neso requires three different voltages, a 3.3V, a 1.8V supply, and a 1.3V supply. Onboard regulators derive these voltages from the USB/Ext power supply.

The bitstream can be generated for Neso in Vivado by following the steps below:

Step 1:  It is recommended to generate .bin file along with .bit file. Right-click on “Generate Bitstream” under the “Program and Debug” section of the Flow Navigator window and click “Bitstream Settings”.

Step 2: Select “-bin_file” option in the dialog window and click “Apply” and then “OK”.

Step 3: Finally click “Generate Bitstream”.

Neso Artix 7 FPGA Development Board features an onboard JTAG connector which facilitates easy reprogramming of SRAM and onboard SPI flash through JTAG programmer like “Xilinx Platform cable USB”. Following steps illustrate how to program FPGA on Neso using JTAG.

Step 1: By using JTAG cable, connect Xilinx platform cable USB to Neso and power it up.

Step 2: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 3: If the device is detected successfully, then select “Program Device” after right clicking on the target device “xc7a100t_0 (1)” as shown below.

Step 4: In the dialog window which opens up, Vivado automatically chooses correct bitstream file if the design was synthesized, implemented and bitstream generated successfully. If needed, browse to the bitstream which needs to be programmed to FPGA. Finally, click “Program”.

A .bin or .mcs file is required for programming Neso Artix 7’s onboard QSPI flash.

Step 1: Open Vivado Project. Click on “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window.

Step 2: If the device is successfully detected, then right-click on the “xc7a100t_0 (1)”. Select “Add Configuration Memory Device” as shown below.

Step 3: Select the memory device “mt25ql128-spi-x1_x2_x4 (which is equivalent to n25q128-3.3v-spi-x1_x2_x4)”, then click OK.

Step 4: After completion of Step 3, a dialog box will open. Click OK.

Step 5: Browse to the working .bin file or the .mcs file (whichever applicable) and click OK to program as shown below. If programming is successful, a confirmation message will be displayed.

For steps on how to program Neso using Tenagra, refer the Getting started with Tenagra FPGA System Management Software article.

Neso Revision V1: Neso Schematics

Neso Revision V2: Neso Schematics

Neso Revision V1: Neso GPIO Easy Reference

Neso Revision V2: Neso GPIO Easy Reference