Vivado Design Suite by Xilinx is used for synthesis and analysis of HDL designs with additional features for SOC development and high-level synthesis. Xilinx recommends use of Vivado Design Suite for new designs with Ultra scale, Virtex-7, Kintex-7, Artix-7 and Zynq-7000. Complete pack of Vivado Design Suite contains Vivado High-Level Synthesis, Vivado Simulator, Vivado IP Integrator and Vivado TCL Store. We will be using Vivado IP Integrator alongside Vivado SDK to create our “Hello World” project for Neso Artix 7 FPGA Module. The design will contain a Microblaze soft processor and peripherals connected together by AXI bus. Thanks to the excellent tools provided by Xilinx, most of the design can be done without writing any code at all.
What is Microblaze?
Microblaze is a 32 bit soft processor IP developed by Xilinx for their mid – high end FPGA devices. Microblaze is compatible with Xilinx’s 6 and 7 series devices such as Spartan 6, Artix, Kintex, Virtex and Zynq devices. More information and resources including datasheet for Microblaze can be found at Xilinx’s Microblaze page. Microblaze IP is bundled with Xilinx IP integrator. Microblaze based embedded design can use either PLB or AXI as the bus system. Since Xilinx is planning to phase out PLB and keep only AXI in the future, we will stick with AXI for our designs. Advanced knowledge of Microblaze or AXI is not a prerequisite to follow this article and build a working system successfully.
What is AXI?
AXI stands for Advanced eXtensible Interface. AXI is a bus interconnect based on ARM’s popular AMBA bus architecture. In a Microblaze system AXI connects the microprocessor to all peripherals in the system. The only exception is Block RAM which is attached to the processor through LMB (Local Memory Bus). AXILite is available for connecting low throughput peripherals to the system such as UART, GPIO etc.… AXILite uses less logic resources on FPGA compared to AXI. Usually AXI is used to connect high throughput peripherals such as DDR memory, Ethernet etc… Again, a detailed understanding of AXI is not required for following this article. But for the curious readers, AXI Reference Guide is available here.
Neso Artix 7 FPGA Module
Neso Artix 7 FPGA module is the first product in a series of Xilinx 7 Series FPGA based products. Neso is pin compatible with Numato Lab’s Saturn Spartan 6 FPGA module and can replace Saturn with no hardware changes in most cases. Neso offers built in USB interface that can be used to program the board as well as do debugging or data transfer with the host. With a XC7A100T FPGA on board, Neso is a great choice for learning, product development and OEM integration.
Neso Artix 7 FPGA Module Specification
|FPGA Device:||XC7A100T - CSG324|
|Number Of GPIOs (Max):||140|
|Configuration Options:||JTAG, USB|
|Primary Clock Frequency:||100MHz|
Tools and Prerequisites
- Neso Artix-7 Development Board.
- Vivado Design Suite with SDK installed. (Preferred 2015.2 and above)
- Xilinx Platform Cable USB II.
- FT_Prog tool for configuring on-board FT2232H USB Serial converter (download and install from FTDI website).
Creating Microblaze based Hardware Platform for Neso
The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with Microblaze soft processor using IP integrator. Numato Lab’s Neso Artix 7 FPGA Module is used in this example but any compatible FPGA platform can be used instead with minor changes to the steps. Screenshots are added wherever possible to make the process easier to the reader.
Start Vivado Design Suite, and select Create New Project from Quick Start menu. The project wizard will pop up. Press next on window to proceed with creating the project.
Type in a name for the project and save it at preferred location. This examples calls the project “NesoArtix7” but feel free to use any name. Select the check box below to keep all project files in a single folder. The image below shows the settings for the example project. Click next to continue.
At the project type selection step, select RTL Project. Click next to proceed.
At the “Default Part” step, select “Boards” and then select Numato Lab Neso Artix 7 FPGA Module and then click next. If Neso is not displayed in the boards list, you will need to install Neso board support files appropriately and retry this step. You can download Neso support files for Vivado from here.
Continue the wizard and finish creating the project. When the new project wizard exits, a new project will be opened up in Vivado with the settings you have selected with the wizard.
Under Flow Navigator, select “Create Block Design” in IP Integrator. Give an appropriate name to design. We will call it NesoDesign for example. Select the “Board” tab on the bottom. The default peripherals available for the selected board (Neso Artix 7 FPGA Module in our case) will be displayed.
Add System Clock, USB UART and DDR3 SDRAM to the design by double clicking on the corresponding peripherals listed. Then go to Design window, right click and select “Add IP” from the popup menu. Search for Microblaze and AXI Timer IPs and add them to design by double clicking on them.
Double click on clock IP and configure it with the settings as shown below.
Remove existing connection to sys_clk_i if any and connect clk_out2 net on the clocking Wizard to sys_clk_i on MIG block as shown in the image below.
Click on “Run Block Automation” on the top left corner of the window to complete the design. Select the settings as shown in the picture below. Click OK for Vivado to automatically configure the blocks for you. Once Block Automation is complete, run “Connection Automation” so Vivado can connect the blocks together to make a complete system.
Connect interrupt output lines from AXI Timer and UARTLite to the Concat block as shown in the picture below. The blocks in question are highlighted in orange.
Right click on the design in the sources window and select “Create HDL Wrapper” from the popup menu. Click OK on the window that appears to finish generating wrapper.
Now click on the “Run Implementation” button (the green arrow) on the main tool bar. Vivado will now synthesize and implement the design. Status of implementation process will be shown in the log window.
Once implementation is complete, click the “Generate Bitstream” button next to the implementation button to generate the bitstream for the design.
Now that the design is implemented successfully, we need to export the bitstream and other related files to be used with SDK. On the file menu, select Export > Export Hardware.
Launch SDK from File menu. You may choose to use the local project directory as SDK workspace or select another directory if appropriate. Once SDK window appears, select “Application Project” from the File menu. Type in a project and select “Hello World” template from the list of available templates.
Once the project is created, SDK will automatically run a build. If that didn’t happen for any reason, run a build manually. Once the build is complete successfully, power up Neso Artix 7 FPGA Module and connect Xilinx Platform USB cable and Micro USB cable for Serial debugging to the board. Make sure to configure channel B of the onboard FT2232H USB – Serial device as virtual communication using FT_Prog. The process is very similar to that of Saturn and details are available here.
Program the board by selecting “Program FPGA” under “Xilinx Tools” menu. Open the serial port corresponding to NESO on your operating system using your preferred Serial Terminal software such as HyperTerminal, Tera Term etc.. Now run the application bu click in on the Run icon on the main toolbar. Select “Launch On Hardware” when asked as shown in image below.
Open any serial terminal and connect to the COM Port corresponding to Neso board. If everything went well, the application running on the board should print “Hello World” over the USB UART and should be displayed on the Serial Terminal application.