Introduction
In this article, we’ll explore the process of creating a simple “Hello World” project using Vivado IP Integrator and Vitis Unified IDE for the Mimas A7 FPGA Development Board. Our design will feature a MicroBlaze soft processor, which will be integrated with various peripherals through the AXI bus. Although MicroBlaze designs can utilize either PLB or AXI bus systems, we’ll focus on the AXI bus for this tutorial. For detailed information on MicroBlaze and additional resources, including the datasheet, please visit Xilinx’s dedicated MicroBlaze page.
Mimas A7 FPGA Development Board
Mimas A7 FPGA Development Board is the product in a series of Xilinx 7 Series FPGA-based products. Mimas A7 offers a built-in USB interface that can be used to program the board as well as do debugging or data transfer with the host. With an XC7A50T FPGA on board, Mimas A7 is a great choice for learning, product development and OEM integration.
Prerequisites:
Hardware:
- Mimas A7 FPGA Development Board.
- Xilinx Platform Cable USB II JTAG debugger.
- USB A to USB Type B cable.
Software:
- Vivado Design Suite 2024.1
- Vitis Unified IDE 2024.1.
Creating Microblaze based Hardware Platform for Mimas A7
The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with MicroBlaze soft processor using an IP integrator. Numato Lab’s Mimas Artix 7 FPGA Development Board is used in this example, but any compatible FPGA platform can be used with minor changes to the steps. Screenshots are added wherever possible to make the process easier for the reader.
Step 1:
Download and install Vivado Board Support Package files for Mimas A7 from here.
Step 2:
Start Vivado Design Suite, and select “Create Project” from Quick Start section. The project wizard will pop up. Press next to proceed with creating the project.
Step 3:
Enter a name for the project and save it at a suitable location. Check the option “Create project subdirectory”. Click Next to continue.
Step 4:
In the Project Type window, select RTL Project and check the option “Do not specify sources at this time”. Click Next.
Step 5:
In the Default Part window, select “Mimas_A7_50T” from the Boards option. If Mimas_A7_50T is not listed, make sure board support files are installed correctly. Click Next to continue.
Click Finish to complete creating a new project. A new project will be created by Vivado with the selected settings.
Step 6:
In the Flow Navigator panel, select Create Block Design under IP INTEGRATOR. Enter a name for the block design and click OK. An empty block design will be created.
Step 7:
Click the Board tab. The default peripherals available for the Mimas A7 board will be displayed.
Step 8:
Add DDR3 SDRAM and USB UART to the design by double-clicking the corresponding peripherals. In the Diagram window, right-click and select “Add IP” from the popup menu. Search for “MicroBlaze” ,”clocking wizard” & “AXI Timer” and add them to the design by double-clicking them.
Step 9:
Double click on “Clocking Wizard” IP and select “CLK_IN1” as “sys clock“.
customize “Output Clocks” settings as shown in the following image and click “OK”.
Step 10:
Remove existing ‘sys_clk_i’ connection and input port (if any) and connect ‘clk_out2‘ net on the clocking Wizard to ‘sys_clk_i’ of the ‘MIG 7 Series’ block as shown in the following image.
Step 11:
Click “Run Block Automation” present in the “Designer Assistance available” bar on the top left corner of the window to complete the design. Select the settings as shown in the following image. Click “OK” for Vivado to automatically configure the blocks for you. Once Block Automation is complete, run “Connection Automation” so Vivado can connect the blocks to make a complete system.
Step 12:
Connect interrupt output lines from “AXI Timer” and “UARTLite” to the “Concat” block as shown below figure. Select the “Validate Design” option from the Tools menu to make sure that connections are correct.
Step 13:
Right-click “Hello_world” in the “Sources” window, and select “Create HDL Wrapper” from the popup menu. Click “OK” on the window that appears to finish generating a wrapper.
Step 14:
Click “Generate Bitstream” under the “Program And Debug” section to synthesize, implement and generate a bitstream.
Step 15:
After generating the bitstream successfully, select Export -> Export Hardware from the File menu. Click Next.
Select the “include bitstream” checkbox and click Next.
Provide the XSA file name and save it at a suitable location. Click Next and click Finish in the next dialog box.
Step 16:
Select Launch Vitis IDE from the Tools menu.
Step 17:
After Vitis Unified IDE window opens, click on “Open Workspace” and select necessary folder to keep the Vitis files.
Step 18:
Create a new platform for the project, by selecting “Create Platform Component”, click “Next”, in the Flow tab select the XSA file saved using the step 15 and finally click “Next” and “Finish” respectively.
After successful creation of the platform, build the platform.
Step 19:
Next create the Helloworld Application component by selecting the “Helloworld” template from the “examples”,
In “Create Application Component” tab specify project name and location, click “Next” 
Select newly created Platform and click “Next”.
Select the domain as “Standalone_microblaze_0” and click “Next” and click on “Finish”
When the Helloworld project is added successfully, build the project manually.
Step 20:
Once the build is completed successfully, power up Mimas A7 FPGA Development Board using an Xilinx Platform USB cable to the board.
Step 21:
Program the FPGA on Mimas A7 with a simple boot loop program by selecting the Program Device option from the Vitis menu.
Once the “Program Device” window opens click on “Program“.
Step 22:
Meanwhile, open any serial terminal program (such as PuTTY, Teraterm etc) and open the port corresponding to Mimas A7 with a 9600 baud rate (the default baud rate given in UART IP). Program the board by selecting the “Run”.
Step 23:
If everything went well, the application running on the board should print “Hello World” over the UART and should be displayed on the Serial Terminal application.
