So far we learned a few things about Verilog and how to create a module in Verilog and run a simulation. While simulation can tell us a lot of things about the correctness of our module, there is nothing like putting it on a piece of hardware and seeing it working. In this part of the tutorial, we will walk you through the steps for synthesizing the module and implementing it on Mimas S7 Lite hardware.
As mentioned in part 3 of this tutorial, the test bench code is used only for simulation. To synthesize our module, we have to remove the test bench code. For those who don’t know, HDL Synthesis is the step where the HDL ( Verilog/VHDL or any other HDL for that matter) is interpreted and an equivalent hardware topology is generated. This hardware topology will be very specific to the target FPGA selected. Synthesis is a very complex process and we don’t need to know the internals to get our simple module up and running.
We will use the Mimas S7 Lite to implement our module. Mimas S7 Lite board has a Xilinx Spartan 7 FPGA, Nine 6×2 Header, and a few other peripherals on board. The exact FPGA part number used on this board is XC7S50-1CSGA324C. The image below shows the part of the schematics where FPGA IOs for LEDs and Push Button Switches are connected. We will use two Push Button Switches and one LED to implement our logic.
Let’s come back to our module and think about how we can implement the same on the hardware. The module in question is an AND gate. As we know, the output of an AND gate is high only when both the inputs are high and the output is low if any of the inputs are low. We can have many possible hardware configurations to test this module. The easiest would be with a switch and an LED. See the proposed hardware configuration in the picture below.
In the above diagram, two switches are connected as inputs. The output is connected to an LED. Let’s take a moment to understand how this circuit is going to behave. When the switch is in an open position, there will be a positive voltage i.e., a logic 1 at the input of the AND gate, and when the switch is closed position there will be no voltage at the input of the switch. In active low circuits like the one in Mimas S7 Lite, the switch is active when the input is low. When both the switches (Input A & B) are pressed at the same time the output (Y) will be high. If only one of the switches is pressed or if no switches are pressed then the output will be low.
Now we know the basic hardware requirements. We need the following in our prospective hardware.
- An input-capable IO with a switch attached.
- An output-capable IO with an LED attached.
Let’s take a closer look at the Mimas S7 lite FPGA Development Board. The following image shows the LED and switch we are planning to use on Mimas S7 Lite.
As we see in the image above, Mimas S7 Lite has Two general-purpose push button switches and eight LEDs for the user’s convenience. We can now take a look at the Mimas s7 lite schematics and learn a little bit more about where the switches and LEDs are connected. We will use switches SW1 and SW2 and LED “LD0” for our purpose. Looking through the schematics reveals that switches SW1 and SW2 are connected to IO A11 and D10. LD0 is connected to A10 of the FPGA respectively.
We now have a Verilog module that we want to implement and we have selected a hardware platform and decided what IOs to use for implementation. Let us revisit our module. I’m reposting the module code here with a few changes since the switches in Mimas S7 Lite are active low, the inputs must be inverted for the switches to be active.
module myModule(a,b,y); input wire a; input wire b; output wire y; assign y = ~a & ~b; endmodule
Our module has three ports. Port A and B are the input and Port Y, which is the output. An attentive reader would be asking now, how are we going to attach Port A and Port B to A11 and D10 of the hardware and Port Y to A10 of the hardware? We will do this by defining user constraints. User constraints tell the router and the placement logic (which is a part of the HDL synthesizer) on which physical pins the module signals are to be connected. We make a list of constraints place it in a file and include that file in the project. This file is called a User Constraints File. For Xilinx Vivado tools, it is a text file with a .xdc extension.
To create the constraints file, follow the steps below:
Step 1 : Go to “Add Sources” under the Flow Navigator –> PROJECT MANAGER window, select the “Add or create constraints” and click “Next”.
Step 2 : Click on “Create file” and give a name for the XDC and select “File type” as “XDC”. Click “OK” and then “Finish”.
Step 3 : The XDC file is now created and is available in the Sources –> Constraints. Double-click on it to open.
Now the constraints file for the project is created. The constraints used in our project are provided below. Copy and paste these constraints in the constraints file.
set_property -dict { PACKAGE_PIN "A11" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { a }];
set_property -dict { PACKAGE_PIN "D10" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { b }];
set_property -dict { PACKAGE_PIN "A10" IOSTANDARD LVCMOS33 SLEW FAST} [get_ports { y }];
Now we have pretty much everything we need to synthesize the design and test it.
Step 4 : Right-click on “Generate Bitstream” in the Flow Navigator panel. Select the “Bitstream Settings” and check the “-bin_file”. Click “Apply” and then “OK”.
Now click on Generate Bitstream. Click “OK” on the following window that appears. The bitstream generation process may take a while.
Step 5 : Once the bitstream generation is completed, if everything goes well and there are no errors, the following window will be displayed.
If there are any errors or warnings, you can check them in the “messages” window.
Now download myModule.bin (should be in the project directory if everything goes well) to the Mimas S7 Lite FPGA board. Please see the Mimas S7 Lite User manual to find more information about downloading output binary files to Mimas S7. Once downloading is complete, press the switch SW1 and SW2 at the same time to see LED0 light up.
Download the complete Xilinx Vivado Implementation project for Mimas S7
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