HDMI Output Example Design for Mimas S7 Lite

Introduction:

HDMI (High-Definition Multimedia Interface) represents a significant advancement over the older VGA standard by offering a digital solution that integrates both high-resolution video and audio into a single interface. Unlike VGA, which relies on analog signals, HDMI uses digital transmission to deliver superior picture and sound quality. HDMI achieves this by transmitting pixel data serially at ten times the pixel clock frequency through TMDS (Transition Minimized Differential Signaling). This method reduces the number of signal transitions, which helps minimize potential data errors and maintains signal integrity.

The article focuses on demonstrating DVI-D output through the Mimas S7 Lite FPGA Module. DVI-D, or Digital Visual Interface – Digital, is a variant of HDMI and shares the same electrical and physical layer specifications. As a result, HDMI cables can also carry DVI-D signals, meaning that HDMI monitors are fully compatible with DVI-D outputs.

Prerequisites:

Hardware:

Mimas S7 Lite
HDMI Expansion Module
HDMI cable and a compatible monitor

Software:

Xilinx Vivado Design Suite 2024.1

Step 1:

Download and install Vivado Board Support Package files for Mimas S7 Lite from here. Follow the “readme” in the link on how to install Vivado Board Support Package files for Numato Lab’s boards.

Step 2:

Start Vivado Design Suite, and select “Create Project” from Quick Start section. The project wizard will pop up. Press next to proceed with creating the project.

Step 3:

Type in a project name and save it at a convenient location. For this example “HDMI” is used as project name, but feel free to use any name. Select the check box below to keep all project files in a single folder. The image below shows the settings for the example project. Click “Next” to continue.

Step 4:

Choose “RTL Project” as project type and check the option “Do not specify sources at this time”.

Step 5:

At the “Default Part” step, select “Boards” and choose Vendor as “numato.com”. Select “Mimas_S7_Lite” and click “Next”. If Mimas_S7_Lite is not displayed in the boards list, you will need to install Mimas_S7_Lite board support files correctly.

Step 6:

Then in the Sources tab, Right-click ‘Design Sources’ and click ‘Add Sources’. It will open a new ‘Add Sources’ window.

Once the “Add Sources” window opens select “Add or create design sources” and click on “Next“.

Step 7:

Download and extract the RTL source files from here and add them to the project by selecting ‘Add Files’ in the “Add or Create Design Sources” tab and click on “Finish“.

The HDMI interface has 3 pairs of differential data signals and 1 pair of differential clock signals:

data_p[2:0] & data_n[2:0] : These are HDMI/DVI differential signals carrying the video data to be displayed on screen.
clk_p & clk_n : HDMI pixel clock differential pair of signals.

First, VGA signals are generated inside vga module. Then the VGA signals are encoded to 10-bits per channel and the data is then serialised to 10x of pixel clock rate. Finally the three channels along with pixel clock are driven out using TMDS differential drivers.

In the top module (dvid_test), the two submodules dvid and vga are instantiated. Clocking IP (clocking wizard) is used to generate clocks for VGA and DVI-D.

dvid_test: In this module, a “Clocking Wizard” IP core is instantiated to generate required clocks for VGA and DVI-D. A 100MHz clock from the onboard oscillator is provided as input, and following clocks are derived from it:

clk_vga: 25MHz clock. This is the pixel clock frequency for 640×480@60Hz VGA resolution.
clk_dvi & clk_dvin : 125 MHz clocks. clk_dvin is 180 degrees out of phase to clk_dvi. These clocks are used for serialization using ODDR2.

vga: VGA signals are generated in this module. This design generates VGA at 640×480@60 Hz resolution.

dvid: VGA signals and clocks are given as input to this module and the DVI TMDS signals are generated as the output. It uses TMDS_encoder module to generate TMDS signals. TMDS uses 8b/10b encoding in which the 8-bit color data (red, green & blue) generated in VGA module is converted to 10 bits. Then this data is serialised using ODDR2 (Double Data Rate primitive). The 10-bit TMDS data is generated at 25 MHz. ODDR2 uses 5 times the frequency of pixel clock (i.e. 125MHz) to serialize the 10-bit encoded data. Note that ODDR2 serialises 2-bits in 1 clock cycle of 125MHz clock. This serialised data is converted into differential signals in top module (dvid_test) using OBUFDS drivers.

Step 8:

Add Clocking Wizard by clicking on IP catalog in Project Manager, type ‘clocking’ in search box and double-click ‘Clocking Wizard’ IP. It will open customisation window for ‘Clocking Wizard’.

Step 9:

In ‘Clocking Options’ tab, give Component Name as ‘clocking’ and primary clock port name as ‘clk_in’.

In ‘Output Clocks’ tab, enable 3 output clocks and provide their name, frequency as well as phase as shown in the image below. Click ‘OK’.

Step 10:

In Sources tab of Vivado, Right-Click on ‘Constraints’ and click ‘Add Sources’.

Step 11:

Once the “Add Sources” tab opens select “Add or create constraints” and click on “Next“.

Click on ‘Create File’ and give ‘HDMI’ as File name. Click ‘OK’ and ‘Finish’.

Step 12:

Copy the following constraints in your constrains file and save it.

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
##Clock Signal
set_property -dict { PACKAGE_PIN "D14"    IOSTANDARD LVCMOS33 } [get_ports { clk_in }];
set_property -dict { PACKAGE_PIN "T14"    IOSTANDARD LVCMOS33 } [get_ports { reset }]; 
###HDMI out  
set_property -dict { PACKAGE_PIN "U1"    IOSTANDARD TMDS_33  } [get_ports { data_n[0] }];  
set_property -dict { PACKAGE_PIN "T1"    IOSTANDARD TMDS_33  } [get_ports { data_p[0] }];  
set_property -dict { PACKAGE_PIN "P1"    IOSTANDARD TMDS_33  } [get_ports { data_n[1] }];  
set_property -dict { PACKAGE_PIN "P2"    IOSTANDARD TMDS_33  } [get_ports { data_p[1] }]; 
set_property -dict { PACKAGE_PIN "T2"    IOSTANDARD TMDS_33  } [get_ports { data_n[2] }];  
set_property -dict { PACKAGE_PIN "R3"    IOSTANDARD TMDS_33  } [get_ports { data_p[2] }]; 
set_property -dict { PACKAGE_PIN "R1"    IOSTANDARD TMDS_33  } [get_ports { clk_n}]; 
set_property -dict { PACKAGE_PIN "R2"    IOSTANDARD TMDS_33  } [get_ports { clk_p}];

Step 13:

In Project Manager tab, Click on ‘Generate Bitstream’.

Step 14:

Once the bitstream is successfully generated, close any “Bitstream Generation Completed” dialog which comes up asking for what to do next.

Step 15:

Set up the hardware for testing the design. For this, Connect ‘Header P1 ’ of HDMI Module to ‘Header P4’ of Mimas S7 Lite. connect HDMI cable between HDMI Expansion module and the monitor. Finally, connect USB type ‘C’ Cable for powering up Mimas S7 Lite.

Step 16:

Now click ‘Open Hardware Manager’ to program the FPGA.

Step 17:

Click on ‘Open target’ and ‘Auto Connect’.

Step 18:

Right Click on the device (xc7s50_0) and select “Program Device” option.

Step 19:

Click “Program” and observe the output.

Step 20:

Once Mimas S7 Lite is successfully programmed, it should begin generating HDMI signals and the monitor should display a colorful pattern at 640×480 @ 60Hz resolution.

That was it! You can play with the vga module to output different patterns and try to generate higher resolutions as well.

Mimas S7 Lite