Introduction:
Ethernet is a Link Layer Protocol in the TCP/IP protocol stack between the physical and data link layer. It is the most widely used protocol for Local Area Networks (LANs). Every device on Ethernet is assigned a unique MAC address for communication. Gigabit Ethernet refers to various technologies developed for transmitting Ethernet frames at the rate of gigabits per second. The Reduced Gigabit Media-Independent Interface (RGMII) is used to interface Ethernet IP core on FPGA with the Gigabit Ethernet PHY chip (RTL8211E) on Mimas A7. The Media Access Layer converts the packets into a stream of data to be sent while the Physical Layer converts the stream of data into electrical signals. RGMII provides a media-independent interface so that there is compatibility between MAC and PHY irrespective of the hardware used. In this tutorial, the Numato Lab Mimas A7 FPGA Development Board is used to demonstrate a TCP/IP echo server application. The echo server application runs on light-weight IP (lwIP) TCP/IP stack.
Prerequisites:
- Hardware:
- Mimas A7 FPGA Development Board
- Cat 6 Ethernet Cable
- Xilinx Platform Cable USB II JTAG
- USB 2.0 B-type cable
- 5V-12V DC Power Supply
- Software:
- Xilinx Vivado Design Suite 2018.2 or later
- Telnet Application
- Serial Terminal (PuTTY, Tera Term, etc.)
Let’s get Started
Step 1:
Download and install Vivado Board Support Package files for Mimas A7 from here. Follow the README.md file on how to install Vivado Board Support Package files for Numato Lab boards.
Step 2:
Open Vivado Design Suite, go to File->Project->New. The “New Project” window will open. Click “Next”.
Enter a name for the project and save it at a suitable location. Select the option “Create project subdirectory”. Click “Next” to continue.
Step 3:
In the “Project Type” window, select “RTL Project” and select “Do not specify sources at this time” box that appears. Click “Next”.
Step 4:
In the “Default Part” step, select “Mimas_A7_50T” from the “Boards” option. If Mimas_A7_50T is not listed, make sure board support files are installed correctly. Click “Next” to continue.
Click “Finish” to complete creating a new project. A new project will be created by Vivado with the selected settings.
Step 5:
Under “Flow Navigator” panel, select “Create Block Design” under “IP INTEGRATOR”. Enter a name for the block design and click “OK”. An empty block design will be created.
Step 6:
Click the “Board” tab. The default peripherals available for the Mimas A7 board will be displayed.
Drag and drop System Clock, USB UART, DDR3 SDRAM, and Gigabit Ethernet PHY peripherals into the block design.
In the “Diagram” window, click “Add IP” (refer the image above) and search for Microblaze, AXI Timer, and AXI Direct Memory Access IPs. Add each of these to the design by double-clicking on their names on the list.
Step 7:
Double click on Clocking Wizard IP block and change the settings as shown below. In the “Output Clocks” section, set clk_out1 frequency to 100 MHz, clk_out2 to 200 MHz, and clk_out3 to 125 MHz. Click “OK” to customize the IP.
Step 8:
Select AXI Uartlite IP and customize it as follows.
Step 9:
Click “Run Block Automation”. Change the settings as shown below. Select the “Interrupt Controller” checkbox. Click “OK” to proceed.
Step 10:
Click “Run Connection Automation”. Select the “All Automation” option and click “OK”. Vivado will automatically add new blocks such as AXI Interrupt Controller and Concat to the design. Ensure that sys_clk_i of Memory Interface Generator is connected to clk_out2.
Step 11:
Customize the concat IP block as shown below.
Concat block will get interrupt inputs from UART, AXI Timer, AXI DMA and AXI Ethernet subsystem. Route the following connections to the inputs of Concat block (order does not matter) :
- interrupt on AXI Uartlite block
- interrupt on AXI Timer block
- mm2s_introut and s2mm_introut on AXI Direct Memory Access block
- interrupt and mac_irq on AXI 1G/2.5G Ethernet Subsystem
Make sure that the final design looks as shown above.
Step 12:
Select “Validate Design” option from Tools menu to make sure that connections are correct.
Step 13:
In the Sources window, right click on the design and select “Create HDL Wrapper”. Click “OK” in the dialog box that appears.
Step 14:
Select “Run Synthesis” followed by “Run Implementation”. If the design is implemented successfully, select “Generate Bitstream”.
Step 15:
After generating the bitstream successfully, select “Export -> Export Hardware” from the File menu. Select “include bitstream” checkbox and click “OK”.
Step 16:
Select “Launch SDK” from the File menu. Select workspace as “Local to project” and click OK to launch the Xilinx SDK.
Step 17:
Select “Application Project” from the File menu. Type in a project name, select hardware platform and click “Next”.
Select “lwIp Echo Server” template from the list of available templates and click “Finish”.
Step 18:
Select “Board Support Package Settings” from the “Xilinx” menu. Select lwip library, change the “dhcp options” to “false” and ensure that “debug options” are “false”.
Select “phy_link_speed” in temac_adapter_options as “CONFIG_LINKSPEED1000”.
After changing the library settings, click “OK”. SDK will update the BSP automatically. If that didn’t happen for any reason, run a build manually.
Step 19:
Once the build is completed successfully, power up Mimas A7 FPGA Development Board using external DC power supply and connect Xilinx Platform USB cable to the board.
Step 20:
Program the FPGA on Mimas A7 with a simple boot loop program by selecting the “Program FPGA” option from the “Xilinx” menu.
Step 21:
Open the COM port corresponding to Mimas A7 in any serial terminal (PuTTY, Tera Term, etc.) with 115200 baud-rate. Now, right click on the .elf file in the Project Explorer and select “Launch on Hardware” as shown below.
Observe the details displayed on the serial terminal.
Step 22:
Connect Ethernet cable to the board and the other end to PC Ethernet port. Go to Control Panel. Select “Network and Sharing Centre” option in “Network and Internet”. Select “Change adapter settings”. Right click on Ethernet, click properties and select “IPv4”. Change the IPv4 address to 192.168.1.15 (any IP address can be used) and default gateway to 192.168.1.1.
Step 23:
Open a telnet session with IP Address 192.168.1.10 (IP address as per main.c) at port 7, give input through keyboard and observe the output. If you enter a character from the keyboard, you can observe the transmitted and echoed characters on telnet as shown.
