Introduction
Vivado Design Suite by Xilinx is used for synthesis and analysis of HDL designs with additional features for SOC development and high-level synthesis. Xilinx recommends use of Vivado Design Suite for new designs with Ultra scale, Virtex-7, Kintex-7, Artix-7 and Zynq-7000. Complete pack of Vivado Design Suite contains Vivado High-Level Synthesis, Vivado Simulator, Vivado IP Integrator and Vivado TCL Store. We will be using Vivado IP Integrator alongside Vitis to create our “Hello World” project for Neso Artix 7 FPGA Module. The design will contain a Microblaze soft processor and peripherals connected together by AXI bus. Thanks to the excellent tools provided by Xilinx, most of the design can be done without writing any code at all.
What is Microblaze?
Microblaze is a 32 bit soft processor IP developed by Xilinx for their mid – high end FPGA devices. Microblaze is compatible with Xilinx’s 6 and 7 series devices such as Spartan 6, Artix, Kintex, Virtex and Zynq devices. More information and resources including datasheet for Microblaze can be found at Xilinx’s Microblaze page. Microblaze IP is bundled with Xilinx IP integrator. Microblaze based embedded design can use either PLB or AXI as the bus system. Since Xilinx is planning to phase out PLB and keep only AXI in the future, we will stick with AXI for our designs. Advanced knowledge of Microblaze or AXI is not a prerequisite to follow this article and build a working system successfully.
What is AXI?
AXI stands for Advanced eXtensible Interface. AXI is a bus interconnect based on ARM’s popular AMBA bus architecture. In a Microblaze system AXI connects the microprocessor to all peripherals in the system. The only exception is Block RAM which is attached to the processor through LMB (Local Memory Bus). AXI Lite is available for connecting low throughput peripherals to the system such as UART, GPIO etc.… AXI Lite uses less logic resources on FPGA compared to AXI. Usually AXI is used to connect high throughput peripherals such as DDR memory, Ethernet etc… Again, a detailed understanding of AXI is not required for following this article. But for the curious readers, AXI Reference Guide is available here.
Neso Artix 7 FPGA Module
Neso Artix 7 FPGA module is the first product in a series of Xilinx 7 Series FPGA based products. Neso is pin compatible with Numato Lab’s Saturn Spartan 6 FPGA module and can replace Saturn with no hardware changes in most cases. Neso offers built in USB interface that can be used to program the board as well as do debugging or data transfer with the host. With a XC7A100T FPGA on board, Neso is a great choice for learning, product development and OEM integration.
Neso Artix 7 FPGA Module Specification
| FPGA Device: | XC7A100T - CSG324 |
| Memory Type: | DDR3 |
| Memory Size: | 2GBits |
| Number Of GPIOs (Max): | 140 |
| Configuration Options: | JTAG, USB |
| Primary Clock Frequency: | 100MHz |
Tools and Prerequisites
- Neso Artix-7 Development Board.
- Vivado Design Suite and Vitis (Version 2023.2.1)
- Xilinx Platform Cable USB II.
- FT_Prog tool for configuring on-board FT2232H USB Serial converter (download and install from FTDI website).
Creating Microblaze based Hardware Platform for Neso
The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with Microblaze soft processor using IP integrator. Numato Lab’s Neso Artix 7 FPGA Module is used in this example but any compatible FPGA platform can be used instead with minor changes to the steps. Screenshots are added wherever possible to make the process easier to the reader.
Step 1:
Launch Vivado Design Suite, go to “File->Project->New” to create a new project. The “New project” wizard will pop up. Click “Next” to continue.
Step 2:
In the “Project Name” wizard, type in a name for the project and save it at a convenient location. For this example, we shall use “Hello_world” as the project name (feel free to use any name). Select the checkbox below to keep all project files in a single folder. Click “Next” to proceed.
Step 3:
In the “Project type” wizard, select “RTL Project” and select the checkbox to skip specifying the source at the moment. Click “Next“.
Step 4:
At the “Default Part” step, select “Boards” and then select Numato Lab Neso Artix 7 FPGA Module and then click next. If Neso is not displayed in the boards list, you will need to install Neso board support files appropriately and retry this step. You can download Neso support files for Vivado from here. Follow the readme in the link on how to install the Vivado board files in your system.
In the next window, click “Finish” to create a new project. When the new project wizard exits, a new project will open up in Vivado with the selected settings.
Step 5:
In the “Flow Navigator” panel, select “Create Block Design” under the IP integrator section. Give an appropriate name (Eg: “Hello_world“) to the design and click “OK“. Select “Board” in the “Block Design” block. The default peripherals available for Mimas A7 Mini Board will be displayed.
Step 6:
Add “System Clock“, “DDR3 SDRAM” and “USB UART” to the design by double-clicking the corresponding peripherals. In the “Diagram” window, right-click and select “Add IP” from the popup menu. Search for “MicroBlaze” & “AXI Timer” and add them to the design by double-clicking them.
Step 7:
Double click “Clocking Wizard” IP and customize “Output Clocks” settings as shown in the following image.
Step 8:
Remove existing “sys_clk_i” connection and input port (if any) and connect “clk_out2” net on the clocking Wizard to “sys_clk_i” of “MIG 7 Series” block as shown in the following image.
Step 9:
Click “Run Block Automation” present in the “Designer Assistance available” bar on the top left corner of the window to complete the design. Select the settings as shown in the following image. Click “OK” for Vivado to automatically configure the blocks for you. Once Block Automation is complete, run “Connection Automation” so Vivado can connect the blocks together to make a complete system.
Step 10:
Connect interrupt output lines from AXI Timer and UartLite to the Concat block as shown in the picture below. The blocks in question are highlighted in red.
Step 11:
Right-click on the design in the “Sources” window, select “Create HDL Wrapper” from the popup menu. Click “OK” on the window that appears to finish generating a wrapper.
Step 12:
Double click on “Generate Bitstream” under “Program And Debug” section to synthesize, implement and generate the bitstream.
Step 13:
Now that implementation and generation of bitstream has been successfully completed, we need to export the hardware along with bitstream. Go to the “File” menu, select “Export->Export Hardware”. 
Select the “include bitstream” checkbox and click Next.
Provide the XSA file name and save it at a suitable location. Click Next and click Finish in the next dialog box.
Step 14:
Launch Vitis IDE. In Vitis IDE window, select Create Application Project and click Next in the dialog box that appears.
Step 15:
In the Platform window, select Create a new platform from hardware tab and import the XSA file which is already created (Provide XSA file location). Click Next
Step 16:
In the Application Project Details window, give an appropriate name for the Vitis Project and click Next. Click Next in the Domain window.
Select the Hello World template from the list of available templates and click Finish.
Step 17:
Once the project is created, the Vitis will automatically run a build. If that didn’t happen for any reason, run the build manually. Once the build is successfully completed, power up Neso Artix 7 FPGA Module and connect Xilinx Platform USB cable and USB A to USB Micro B cable for Serial debugging to the board.
Step 18:
Program the FPGA on Neso A7 with a simple boot loop program by selecting the Program Device option from the Vitis menu.
Step 19:
Open the COM port corresponding to Neso A7 in any serial terminal (PuTTY, Tera Term, etc.) with a 9600 baud rate (the default baud rate given in UART IP). Now, right-click on the .elf file in Project Explorer and select “Launch Hardware” as shown below.
If everything went well, the application running on the board should print “Hello World” over the USB UART and should be displayed on the Serial Terminal application.
