Introduction
Vivado Design Suite by Xilinx is used for synthesis and analysis of HDL designs with additional features for SOC development and high-level synthesis. Xilinx recommends use of Vivado Design Suite for new designs with Ultra scale, Virtex-7, Kintex-7, Artix-7, and Zynq-7000. Complete pack of Vivado Design Suite contains Vivado High-Level Synthesis, Vivado Simulator, Vivado IP Integrator and Vivado TCL Store. We will be using Vivado IP Integrator alongside Vitis to create our “Hello World” project for Skoll Kintex 7 FPGA Module. The design will contain a Microblaze soft processor and peripherals connected together by AXI bus. Thanks to the excellent tools provided by Xilinx, most of the design can be done without writing any code at all.
What is Microblaze?
Microblaze is a 32 bit soft processor IP developed by Xilinx for their mid – high end FPGA devices. Microblaze is compatible with Xilinx’s 6 and 7 series devices such as Spartan 6, Artix, Kintex Virtex and Zynq devices. More information and resources including datasheet for Microblaze can be found at Xilinx’s Microblaze page. Microblaze IP is bundled with Xilinx IP integrator. Microblaze based embedded design can use either PLB or AXI as the bus system. Since Xilinx is planning to phase out PLB and keep only AXI in the future, we will stick with AXI for our designs. Advanced knowledge of Microblaze or AXI is not a prerequisite to follow this article and build a working system successfully.
Skoll Kintex 7 FPGA Module
Skoll Kintex 7 FPGA module is the first product from Numato Lab featuring Xilinx Kintex 7 FPGA. Skoll is pin compatible with Numato Lab’s Saturn Spartan 6 FPGA module and can replace Saturn with no hardware changes in most cases. Skoll offers built in USB2 interface that can be used to program the board as well as do debugging or data transfer with the host. With a XC7K70T FPGA on board, Skoll is a great choice for learning, product development and OEM integration.
Tools and Prerequisites
- Skoll Kintex-7 FPGA Module
- Vivado Design Suite with Vitis. (2023.2.1)
- Xilinx Platform Cable USB II.
- FT_Prog tool for configuring on-board FT2232H USB Serial converter (download and install from FTDI website).
Creating MicroBlaze based Hardware Platform for Skoll K7
The following steps will walk you through the process of creating a new project with Xilinx Vivado and building a hardware platform with MicroBlaze soft processor using the Vivado IP integrator. Numato Lab’s Nereid FPGA Development Board is used in this article but any compatible FPGA platform can be used with minor changes to the steps. Screenshots are added wherever possible to make the process easier for the reader.
Step 1:
Download and install the Vivado Board Support Package files for Nereid from here. Follow the README.md file on how to install Vivado board support files for Numato Lab boards.
Step 2:
Open the Xilinx Vivado Design suite, go to “File -> Project -> New” to create a new project. The “New project” window will pop up. Click “Next”.
Step 3:
In the “Project Name” window, enter a name for the project and save it at a suitable location. Select the option “Create project subdirectory” to keep all the project files in a single folder. For this example, “Hello_world” is used as the project name, but feel free to use any name. Click “Next”.
Now you will see the “Project Type” page as shown below. Select the “RTL Project” and select the option “Do not specify sources at this time”. Click “Next”.
Step 4:
In the “Default Part” window, select the “Boards” tab. Choose the Vendor as “numato.com”, filter the Name “Nereid” and select the board as shown below. Click “Next” to continue. If Nereid is not displayed in the boards list, make sure that the board support files are installed correctly.
In the next window, click “Finish” to complete creating the new project. When the new project wizard exits, a new project will be created by Vivado with the specified settings.
Step 5:
Under the “Flow Navigator” panel, click “Create Block Design” under the IP Integrator section. Enter a name for the block design and click “OK”. An empty block design will be created.
Step 6:
Click the “Board” tab. The default peripherals available for the Nereid board will be listed as shown below.
Add System Clock, DDR3 SDRAM and USB UART to the design by double-clicking the corresponding peripherals. In the Diagram window, right-click and select “Add IP” from the popup menu. Search for “MicroBlaze” & “AXI Timer” and add them to the design by double-clicking them.
Step 7:
Double-click on the “Clocking Wizard” IP block and change the settings as shown below. In the “Output Clocks” section, set clk_out1 frequency to 100 MHz and clk_out2 to 200 MHz. Set “Reset Type” as Active Low and click “OK” to customize the IP.
Step 8:
Remove the existing connection to sys_clk_i of the “MIG 7 Series” block and connect it to clk_out2.
Step 9:
Click “Run Block Automation” present in the “Designer Assistance available” bar on the top left corner of the window to complete the design. Select the settings as shown in the following image. Click “OK” for Vivado to automatically configure the blocks for you. Once Block Automation is complete, run “Connection Automation” so Vivado can connect the blocks to make a complete system.
Step 10:
Connect interrupt output lines from “AXI Timer” and “UARTLite” to the “Concat” block as shown below figure. Select the “Validate Design” option from the Tools menu to make sure that connections are correct.
Step 11:
Right-click “Hello_world” in the “Sources” window, and select “Create HDL Wrapper” from the popup menu. Click “OK” on the window that appears to finish generating a wrapper
Step 12:
Click “Generate Bitstream” under the “Program And Debug” section to synthesize, implement and generate a bitstream.
Step 13:
After generating the bitstream successfully, select Export -> Export Hardware from the File menu. Click Next.
Select the “include bitstream” checkbox and click Next.
Provide the XSA file name and save it at a suitable location. Click Next and click Finish in the next dialog box.
Step 14:
Launch Vitis IDE. In Vitis IDE window, select Create Application Project and click Next in the dialog box that appears.
In the Platform window, select Create a new platform from hardware tab and import the XSA file which is already created (Provide XSA file location). Click Next.
Step 15:
In the Application Project Details window, give an appropriate name for the Vitis Project and click Next. Click Next in the Domain window.
Select the Hello World template from the list of available templates and click Finish.
Step 16:
Once the project is created, the Vitis will automatically run a build. If that didn’t happen for any reason, run the build manually. Once the build is completed successfully, power up Skoll Kintex 7 FPGA Module and connect Xilinx Platform USB cable and Micro USB cable for Serial debugging to the board. Make sure to configure channel B of the onboard FT2232H USB – Serial device as virtual communication using FT_Prog. The process is very similar to that of Saturn and details are available here.
Step 17:
Program the FPGA on Aller with the generated bitstream and simple bootloop firmware by selecting the “Program Device” option from the “Vitis” menu.
Step 18:
Right-click on the .elf file in the Project Explorer and select “Launch on Hardware” as shown below.
If everything went well, the application running on the board should print “Hello World” over the USB UART and should be displayed on the Serial Terminal application.
