Vivado Design Suite – Create MicroBlaze based design using IP Integrator With Nereid Kintex 7 PCI Express Development Board

Introduction

The Vivado Design Suite from Xilinx is used for the synthesis and analysis of HDL designs for Xilinx FPGAs, superseding the Xilinx ISE Design Suite with additional features for SoC development and high-level synthesis. This tool increases the overall productivity for designing, integrating and implementing systems with Xilinx’s UltraScale, 7 series devices, and Zynq-7000. In this article, we’ll be using the Vivado IP Integrator alongside the Vivado SDK to create the classic “Hello World” project for the Nereid Kintex 7 PCI Express FPGA Development Board containing a 32-bit MicroBlaze soft processor and peripherals connected together by the AXI4 bus.

What is MicroBlaze?

MicroBlaze is a 32-bit soft processor IP developed by Xilinx for their mid and high-end FPGA devices. It is compatible with Xilinx’s 6 and 7 series FPGAs. More information on Microblaze can be found at Xilinx’s MicroBlaze page. Advanced knowledge of MicroBlaze or AXI is not a prerequisite to follow this article. Thanks to the excellent tools provided by Xilinx, most of the design can be done without writing any code at all.

What is AXI?

AXI stands for Advanced eXtensible Interface. AXI is a bus interconnect based on ARM’s popular AMBA bus architecture. In a MicroBlaze system, AXI connects the microprocessor to all peripherals in the system. The only exception is the Block RAM which is attached to the processor through the LMB (Local Memory Bus). AXI4-Lite is available for connecting low throughput peripherals to the system such as the UART, GPIO, etc. AXI4-Lite uses fewer logic resources on FPGA compared to AXI. Usually, AXI is used to connect high throughput peripherals such as DDR memory, Ethernet, etc. Again, a detailed understanding of AXI is not required for following this article. But for the curious readers, AXI Reference Guide is available here.

Nereid Kintex 7 PCI Express FPGA Board

The Nereid board from Numato Lab is an easy to use FPGA Development Board with x4 PCIe interface featuring Xilinx’s Kintex 7 FPGA. It also features a high-speed FMC connector enabling the users to add additional features to the board using FMC compliant daughter cards. Thus Nereid is a great choice for both learning as well as high-end applications. Let’s get started!

Prerequisites:

Hardware:

Nereid Kintex 7 PCI Express FPGA Development Board
Xilinx Platform Cable USB II
USB 2.0 Type-A to Micro-B cable
12V DC power supply

Software:

Vivado Design Suite with SDK installed (2018.2 or higher)
Serial terminal application (PuTTY, Tera Term, etc.)

Creating MicroBlaze based Hardware Platform for Nereid

The following steps will walk you through the process of creating a new project with Xilinx Vivado and building a hardware platform with MicroBlaze soft processor using the Vivado IP integrator. Numato Lab’s Nereid FPGA Development Board is used in this article but any compatible FPGA platform can be used with minor changes to the steps. Screenshots are added wherever possible to make the process easier for the reader.

Step 1:

Download and install the Vivado Board Support Package files for Nereid from here. Follow the README.md file on how to install Vivado board support files for Numato Lab boards.

Step 2:

Open the Xilinx Vivado Design suite, go to “File -> Project -> New” to create a new project. The “New project” window will pop up. Click “Next”.

Step 3:

In the “Project Name” window, enter a name for the project and save it at a suitable location. Select the option “Create project subdirectory” to keep all the project files in a single folder. For this example, “Nereid_MicroBlaze” is used as the project name, but feel free to use any name. Click “Next”.

Now you will see the “Project Type” page as shown below. Select the “RTL Project” and select the option “Do not specify sources at this time”. Click “Next”.

Step 4:

In the “Default Part” window, select the “Boards” tab. Choose the Vendor as “numato.com”, filter the Name “Nereid” and select the board as shown below. Click “Next” to continue. If Nereid is not displayed in the boards list, make sure that the board support files are installed correctly.

In the next window, click “Finish” to complete creating the new project. When the new project wizard exits, a new project will be created by Vivado with the specified settings.

Step 5:

Under the “Flow Navigator” panel, click “Create Block Design” under the IP Integrator section. Enter a name for the block design and click “OK”. An empty block design will be created.

Step 6:

Click the “Board” tab. The default peripherals available for the Nereid board will be listed as shown below.

Drag and drop the System Clock, USB UART, and DDR3 SDRAM peripherals into the block design. In the “Diagram” window, click “Add IP” (refer to the image below) and search for MicroBlaze.

Add the MicroBlaze to the design by double-clicking its name in the list. Now, you will have the following blocks in your “Diagram” window.

Step 7:

Double-click on the “Clocking Wizard” IP block and change the settings as shown below. In the “Output Clocks” section, set clk_out1 frequency to 100 MHz and clk_out2 to 200 MHz. Set “Reset Type” as Active Low and click “OK” to customize the IP.

Remove the existing connection to sys_clk_i of the “MIG 7 Series” block and connect it to clk_out2.

Step 8:

Click “Run Block Automation” and change the settings as shown below. Click “OK” for Vivado to automatically configure the blocks for you.

Step 9:

Once the Block Automation completes, click “Run Connection Automation”. Select “All Automation” checkbox and click “OK”. Vivado will now connect the blocks together to make a complete system. Make sure that the final design looks as shown below.

Step 10:

Select the “Validate Design” option from Tools menu to ensure that the connections are correct.

Step 11:

Save the design and then right-click on the block design in the “Sources” window, select the “Create HDL Wrapper” from the popup menu. Click “OK” on the window that appears to finish generating the wrapper.

Step 12:

Select “Run Synthesis” followed by “Run Implementation”. If the design is implemented successfully, then select “Generate Bitstream”.

Step 13:

If the bitstream is generated successfully, we can export the hardware platform along with the bitstream to the Xilinx SDK. Go to “File -> Export -> Export Hardware”, and select “Include bitstream” checkbox in the window that pops up. You may select “<Local to Project>” to export the files to the local project directory or choose another directory, and click “OK”.

Step 14:

Select “Launch SDK” from the File menu. In the window that appears, select the location where the hardware platform was exported as the “Exported location” and select SDK workspace as well. Click “OK” to launch the Xilinx SDK.

In the next section, we will see how to create a basic “Hello World” project using the Xilinx SDK.

Software Development in SDK

The SDK launches and a hardware platform project for the design will be automatically created. The hardware platform specification project will be displayed in the Project Explorer of SDK.