Introduction
Vivado Design Suite is developed by Xilinx and is used for the synthesis and analysis of HDL design with additional features for SOC development and high-level synthesis. Xilinx recommends the use of the Vivado Design Suite for new designs with 7-series and newer FPGAs. The complete Vivado Design Suite pack contains Vivado High-Level Synthesis, Vivado Simulator, Vivado IP Integrator, and Vivado TCL Store. In this article, we will be using Vivado IP Integrator along with Vitis to create the basic “Hello World” project for Narvi Spartan 7 FPGA Module. The design will contain a Microblaze soft processor and peripherals connected together by the AXI bus. Thanks to the excellent tools provided by Xilinx, most of the design can be done without writing any code at all.
What is Microblaze?
Microblaze is a 32-bit soft processor IP developed by Xilinx for their mid and high-end FPGA devices. Microblaze is compatible with Xilinx’s 6 and 7 series devices such as Spartan 6, Artix-7, Kintex-7, Virtex-7 and Zynq-7000 devices. More information and resources including a datasheet for Microblaze can be found at Xilinx’s Microblaze page. The Microblaze IP is bundled with the Xilinx IP integrator. It is not a prerequisite to have any advanced knowledge of Microblaze or AXI to follow this article and build a working system successfully.
What is AXI?
AXI stands for Advanced eXtensible Interface. AXI is an interconnected bus based on ARM’s popular, AMBA bus architecture. In a Microblaze system, the AXI connects the microprocessor to all peripherals in the system. The only exception is the Block RAM which is attached to the processor through the LMB (Local Memory Bus). AXI4-Lite is available for connecting low throughput peripherals to the system such as UART, GPIO, etc. AXI4-Lite uses fewer logic resources on FPGA compared to AXI. Usually, AXI is used to connect high throughput peripherals such as DDR memory, Ethernet, etc. Again, a detailed understanding of AXI is not required for following this article. But for the curious readers, AXI Reference Guide is available here.
Prerequisites:
Hardware:
- Narvi Spartan 7 FPGA Module
- Xilinx Platform Cable USB II JTAG debugger
- USB A to USB Micro B cable
Software:
- Vivado Design Suite with Vitis 2023.2.1.
Creating Microblaze based Hardware Platform for Narvi
The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with a Microblaze soft processor using an IP integrator. Numato Lab’s Narvi FPGA Development Board is used in this example, but any compatible FPGA platform can be used with minor changes to the steps. Screenshots are added wherever possible to make the process easier for the reader.
Step 1:
Open the Vivado Design suite, go to “File->Project ->New” to create a new project. The “New project” window will pop up. Click “Next” to continue.
Step 2:
In the “Project Name” window, type in a name for the project and save it in a convenient location. For this example, “Hello_world” is used as the project name, but feel free to use any name. Select the checkbox below to keep all project files in a single folder and Click “Next” to proceed.
Step 3:
In the “Project type” window, select “RTL Project”, check the option “Do not specify sources at this time” and click “Next”.
Step 4:
At the “Default Part” window, in “Boards” select vendor as “numato.com” and select the board name “Narvi” and click “Next” to continue. If Narvi is not displayed in the boards list, you will need to install Narvi board support files appropriately and retry this step. You can download the Narvi board support files for Vivado from here. Follow the “readme” in the link on how to install the Vivado board files in your system.
In the next window, click “Finish” to create a new project. When the new project wizard exits, a new project will open up in Vivado with the selected settings.
Step 5:
In the “Flow Navigator” panel, select the “Create Block Design” under the IP integrator section. Give an appropriate name to the design and click “OK” (the author used “Hello_world” as the design name). Select “Boards” in the “Block Design” block. The default peripherals available for the Narvi Board will be displayed.
Step 6:
Add “System Clock“, “DDR3 SDRAM” and “USB UART” to the design by double-clicking the corresponding peripherals. In the “Diagram” window, right-click and select “Add IP” from the popup menu. Search for “MicroBlaze” & “AXI Timer” and add them to the design by double-clicking them.
Step 7:
Double click on the Clock IP and make changes as shown below.
Step 8
Remove the existing connection to ‘sys_clk_i’ and connect ‘clk_out2′ net on the clocking Wizard to ‘sys_clk_i’ of ‘MIG 7 Series’ block as shown in the image below.
Step 9:
Click on “Run Block Automation” on the top left corner of the window to complete the design. Select the settings as shown in the image below. Click “OK” for Vivado to automatically configure the blocks for you. Once Block Automation is complete, “Run Connection Automation” so Vivado can connect the blocks together to make a complete system.
Step 10:
Connect interrupt output lines from AXI Timer and UartLite to the Concat block as shown in the picture below. The blocks in question are highlighted in red.
Step 11:
Right-click on the design in the “Sources” window, select “Create HDL Wrapper” from the popup menu. Click “OK” on the window that appears to finish generating a wrapper.
Step 12:
Double click on “Generate Bitstream” under “Program And Debug” section to synthesize, implement and generate the bitstream.
Step 13:
Now that implementation and generation of bitstream has been successfully completed, we need to export the hardware along with bitstream. Go to the “File” menu, select “Export->Export Hardware”.
Select the “include bitstream” checkbox and click Next.
Provide the XSA file name and save it at a suitable location. Click Next and click Finish in the next dialog box.
Step 14:
Launch Vitis IDE. In Vitis IDE window, select Create Application Project and click Next in the dialog box that appears.
In the Platform window, select Create a new platform from hardware tab and import the XSA file which is already created (Provide XSA file location). Click Next
Step 15:
In the Application Project Details window, give an appropriate name for the Vitis Project and click Next. Click Next in the Domain window.
Select the Hello World template from the list of available templates and click Finish.
Step 16:
Once the project is created, the Vitis will automatically run a build. If that didn’t happen for any reason, run the build manually. Once the build is successfully completed, power up Narvi FPGA Development Board and connect Xilinx Platform USB cable and USB A to USB Micro B cable for Serial debugging to the board.
Step 17:
Program the FPGA on Narvi S7 with a simple boot loop program by selecting the Program Device option from the Vitis menu.
Step 18:
Open the COM port corresponding to Narvi S7 in any serial terminal (PuTTY, Tera Term, etc.) with a 9600 baud rate (the default baud rate given in UART IP). Now, right-click on the .elf file in Project Explorer and select “Launch Hardware” as shown below.
If everything went well, the application running on the board should print “Hello World” over the USB UART and should be displayed on the Serial Terminal application.
