Vivado Design Suite – Create Microblaze based design using IP Integrator With Skoll Kintex 7 FPGA Module

Introduction

Vivado Design Suite by Xilinx is used for synthesis and analysis of HDL designs with additional features for SOC development and high-level synthesis. Xilinx recommends use of Vivado Design Suite for new designs with Ultra scale, Virtex-7, Kintex-7, Artix-7, and Zynq-7000. Complete pack of Vivado Design Suite contains Vivado High-Level Synthesis, Vivado Simulator, Vivado IP Integrator and Vivado TCL Store. We will be using Vivado IP Integrator alongside Vivado SDK to create our “Hello World” project for Skoll Kintex 7 FPGA Module. The design will contain a Microblaze soft processor and peripherals connected together by AXI bus. Thanks to the excellent tools provided by Xilinx, most of the design can be done without writing any code at all.

What is Microblaze?

Microblaze is a 32 bit soft processor IP developed by Xilinx for their mid – high end FPGA devices. Microblaze is compatible with Xilinx’s 6 and 7 series devices such as Spartan 6, Artix, Kintex Virtex and Zynq devices. More information and resources including datasheet for Microblaze can be found at Xilinx’s Microblaze page. Microblaze IP is bundled with Xilinx IP integrator. Microblaze based embedded design can use either PLB or AXI as the bus system. Since Xilinx is planning to phase out PLB and keep only AXI in the future, we will stick with AXI for our designs. Advanced knowledge of Microblaze or AXI is not a prerequisite to follow this article and build a working system successfully.

Skoll Kintex 7 FPGA Module

Skoll Kintex 7 FPGA module is the first product from Numato Lab featuring Xilinx Kintex 7 FPGA . Skoll is pin compatible with Numato Lab’s Saturn Spartan 6 FPGA module and can replace Saturn with no hardware changes in most cases. Skoll offers built in USB2 interface that can be used to program the board as well as do debugging or data transfer with the host. With a XC7K70T FPGA on board, Skoll is a great choice for learning, product development and OEM integration.

Tools and Prerequisites

Skoll Kintex-7 FPGA Module
Vivado Design Suite with SDK installed. (2015.2 and above preferred )
Xilinx Platform Cable USB II.
FT_Prog tool for configuring on-board FT2232H USB Serial converter (download and install from FTDI website).

Creating Microblaze based Hardware Platform for Skoll

The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with Microblaze soft processor using IP integrator. Numato Lab’s Skoll Kintex 7 FPGA Module is used in this example but any compatible FPGA platform can be used with minor changes to the steps. Screenshots are added wherever possible to make the process easier to the reader.

Step 1:

Start Vivado Design Suite, and select Create New Project from Quick Start menu. The project wizard will pop up. Press next on window to proceed with creating the project.

Step 2:

Type in a name for the project and save it at preferred location. This examples calls the project “Skoll_Microblaze” but feel free to use any name. Select the check box below to keep all project files in a single folder. The image below shows the settings for the example project. Click next to continue.

Step 3:

At the project type selection step, select RTL Project. Click next to proceed.

Step 4:

At the “Default Part” step, select “Boards” and then select Numato Lab Skoll Kintex 7 FPGA Module and then click next. If Skoll is not displayed in the boards list, you will need to install Skoll board support files appropriately and retry this step. For this download Numato Board Support Package for Vivado from here and copy it to “C:\Xilinx\Vivado\2015.2\data\boards\board_files” assuming your Xilinx is installed in “C:\Xilinx” folder. After copying, you should have a Skoll folder in the directory “board_files”.

Continue the wizard and finish creating the project. When the new project wizard exits, a new project will be opened up in Vivado with the settings you have selected with the wizard.

Step 5:

Under Flow Navigator, select “Create Block Design” in IP Integrator. Give an appropriate name to design. We will call it skoll_microblaze for example. Select the “Board” tab on the bottom. The default peripherals available for the selected board (Skoll Kintex 7 FPGA Module in our case) will be displayed.

Step 6:

Add System Clock, DDR3 SDRAM and USB UART to the design by double clicking on the corresponding peripherals listed. Then go to Design window, right click and select “Add IP” from the popup menu. Search for Microblaze, AXI Timer and AXI Quad SPI IPs and add them to design by double clicking on them.

Step 7:

Double click on clock IP and configure it with the settings as shown below.

Step 8:

Double click on AXI Quad SPI block and change its settings as shown in the figure. Make sure to check the “Enable STARTUPE2 Primitive” option. This option is critical for booting Linux from SPI flash, which is described in another article.

Step 9:

Right click on the SPI_0 port on the AXI Quad SPI block and choose “Make External”. There will now be an external port named SPI_0.

Now we have to add constraints for this external port. Go to Project Manager. In the Sources window, right-click anywhere and select “Edit Constraints Sets”. Add a new constraints file and save the below contents to that xdc file:

#####################################################################
#                          QSPI - Flash                             #
#####################################################################
set_property SLEW FAST [get_ports {spi_0_io0_io}];
set_property IOSTANDARD LVCMOS33 [get_ports {spi_0_io0_io}];
set_property PACKAGE_PIN H18 [get_ports {spi_0_io0_io}]; #IO_L1P_T0_D00_MOSI_14 Sch=SPI_DQ0

set_property SLEW FAST [get_ports {spi_0_io1_io}];
set_property IOSTANDARD LVCMOS33 [get_ports {spi_0_io1_io}];
set_property PACKAGE_PIN H19 [get_ports {spi_0_io1_io}]; #IO_L1N_T0_D01_DIN_14 Sch=SPI_DQ1

set_property SLEW FAST [get_ports {spi_0_ss_io}];
set_property IOSTANDARD LVCMOS33 [get_ports {spi_0_ss_io}];
set_property PACKAGE_PIN L16 [get_ports {spi_0_ss_io}]; #IO_L6P_T0_FCS_B_14 Sch=SPI_CS_N

Step 10:

Remove existing sys_clk_i connections and ports if any and connect clk_out2 net on the Clocking Wizard to sys_clk_i on MIG block as shown in the image below.

Step 11:

Click on “Run Block Automation” on the top left corner of the window to complete the design. Select the settings as shown in the picture below. Click OK for Vivado to automatically configure the blocks for you. Once Block Automation is complete, run Connection Automation so Vivado can connect the blocks together to make a complete system. After Connection Automation is complete and if the “resetn” of Clocking Wizard is left unconnected, then connect it to the “reset” line as shown in the Step 12’s image.

Step 12:

Connect interrupt output lines from AXI Timer and UARTLite to the Concat block as shown in the picture below. The blocks in question are highlighted in orange..

Step 13:

Right click on the design in the sources window and select “Create HDL Wrapper” from the popup menu. Click OK on the window that appears to finish generating wrapper.

Step 14:

Now click on the “Run Implementation” button (the green arrow) on the main tool bar. Vivado will now synthesize and implement the design. Status of implementation process will be shown in the log window.

Once implementation is complete, click the “Generate Bitstream” button next to the implementation button to generate the bitstream for the design.

Step 15:

Now that the design is implemented successfully, we need to export the bitstream and other related files to be used with SDK. On the file menu, select Export > Export Hardware.

Step 16:

Launch SDK from File menu. You may choose to use the local project directory as SDK workspace or select another directory if appropriate. Once SDK window appears, select “Application Project” from the File menu. Type in a project and select “Hello World” template from the list of available templates.

Step 17:

Once the project is created, SDK will automatically run a build. If that didn’t happen for any reason, run a build manually. Once the build is complete successfully, power up Skoll Kintex 7 FPGA Module and connect Xilinx Platform USB cable and Micro USB cable for Serial debugging to the board. Make sure to configure channel B of the onboard FT2232H USB – Serial device as virtual communication using FT_Prog. The process is very similar to that of Saturn and details are available here.

Step 18:

Program the board by selecting “Program FPGA” under “Xilinx Tools” menu. Open the serial port corresponding to Skoll board on your operating system using your preferred Serial Terminal software such as HyperTerminal, Tera Term etc. Now run the application by clicking on the Run icon on the main toolbar. Select “Launch On Hardware” when asked as shown in image below.

Open any serial terminal and connect to the COM Port corresponding to Skoll board. If everything went well, the application running on the board should print “Hello World” over the USB UART and should be displayed on the Serial Terminal application.

Congratulations! You have successfully created a Microblaze based design on Skoll Kintex 7 FPGA Module. Further on, you can also try “Memory Tests” example in the SDK and make sure your DDR3 Memory is working fine.

Skoll Kintex 7 FPGA Module