Introduction
Vivado Design Suite by AMD is used for synthesis and analysis of HDL designs with additional features for SoC development and high-level synthesis. AMD recommends use of Vivado Design Suite for new designs with Ultra scale, Virtex-7, Kintex-7, Artix-7, and Zynq-7000. In this article we will use Vivado to create a basic “DDR3 Memory Test” program for TityraCore Z7 Development board running on Zynq’s ARM processor. We will also demonstrate use of EMIO for routing peripheral signals to programmable logic.
Prerequisites
To follow this article, you would need the following:
- Hardware:
- TityraCore Z7 Development board
- TityraCore Z7 carrier
- AMD Platform Cable II JTAG debugger.
- USB Type C Cable.
- Software:
- AMD Vivado Design Suite 2025.1
- Vitis ide 2025.1
- FT_Prog tool for configuring on-board FT2232H USB Serial converter (download and install from FTDI website)
Let’s get started
The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with Zynq processing system using IP integrator. This article is written for Numato Lab’s TityraCore Z7 Development board, but can be adapted to any other Zynq based platform with minor changes. Screenshots are added wherever possible to make the process easier to the reader.
Step 1:
Start Vivado Design Suite, and select “Create New Project” from Quick Start section. The project wizard will pop up. Press next to proceed with creating the project.
Step 2:
Type in a project name and save it at a convenient location. For this example “Tityra_DDRL” is used as project name, but feel free to use any name. Select the check box below to keep all project files in a single folder. The image below shows the settings for the example project. Click “Next” to continue.
Step 3:
Choose “RTL Project” as project type and check the option “Do not specify sources at this time”.
Step 4:
At the “Default Part” stage, switch to the “Boards” tab and set the vendor to numato.com. Select “Tityra” and click Next.If the Tityra board does not appear in the list, click “Refresh” to update the board catalog. Vivado will then download the latest board files, after which Tityra will become available for selection.
Continue the wizard and finish creating the project. When the new project wizard exits, a new project will be opened up in Vivado with the settings you have selected.
Step 5:
Under Flow Navigator, select “Create Block Design” in IP Integrator. Give an appropriate name to design. We will call it “tityra” for example.
Step 6:
Go to Diagram window, right click and select “Add IP” from the popup menu. Search for ZYNQ7 Processing System. Add it to block design by double clicking.
Step 7:
Click on “Run Block Automation” option on the green bar.
Step 8:
In the “Run Block Automation” window, select the options as in image below and click OK.
Step 9:
Go to “Sources” tab, right click on “tityra” design file and select “Create HDL Wrapper”. Click OK on the window that appears to finish generating wrapper.
Step 10:
Click “Generate Bitstream” under PROGRAM AND DEBUG section and click “Yes” in any subsequent dialog window which comes up.
Step 11:
Once the bitstream is successfully generated, close any “Bitstream Generation Completed” dialog which comes up asking for what to do next , click OK.
Go to File -> Export -> Export Hardware…
Check “Include bitstream”, keep “Export to:” default, and click OK.
Step 12:
Launch Vitis IDE and create a new platform for the project, by selecting “Create Platform Component”, click “Next”, in the Flow tab select the XSA file saved using the step 15 and finally click “Next” and “Finish” respectively.
Step 13:
Give the component name and the platform location and click on “Next”.
Step 14:
In the next tab browse the XSA file , select it , click on “Next”. In the next OS and Processor tab click “Next” and “Finish”.
After successful creation of the platform, build the platform.
Step 15:
Next create the Memory Test Application component by selecting the “Memory Test” template from the “examples”.
In “Create Application Component” tab specify project name and location, click “Next”.
Select newly created Platform and click “Next”.
When the Memory Test project is added successfully, build the project manually.
Once the build is complete successfully, power up TityraCore Z7 development board and connect AMD Platform USB cable and Micro USB cable for Serial debugging to the board. Make sure to change the TityraCore’s Boot Mode to JTAG in the carrier. Please refer to user manual to learn more about configuring Tityra’s Boot Mode.
Step 16:
Program the board by selecting Vitis -> Program Device -> Program. Click Program in the window that opens up.
Step 17:
Open any serial terminal program (such as PuTTY, Teraterm etc) and open the port corresponding to TityraCore at 115200 baudrate.
Step 18:
After FPGA is successfully programmed, click on the “Run” button.
If everything went well, the application running on the board should print the following information over the UART and should be displayed on the Serial Terminal application.
