Mimas AU-Plus FPGA Development Board

Introduction:

Ethernet is a Link Layer Protocol within the TCP/IP protocol stack, residing between the physical and data link layers. It’s the most widely used protocol for Local Area Networks (LANs), with each device identified by a unique MAC address for communication. Gigabit Ethernet offers high-speed data transmission at gigabits per second.

The Reduced Gigabit Media-Independent Interface (RGMII) is employed to interface the Ethernet IP core on the AMD Artix UltraScale+ FPGA of the Mimas AU-Plus board with the Microchip KSZ9031RNX Gigabit Ethernet PHY chip. This setup ensures compatibility between the Media Access Layer (which converts packets into a data stream) and the Physical Layer (which translates the data stream into electrical signals), regardless of specific hardware. In this tutorial, the Numato Lab Mimas AU Plus FPGA Development Board is utilized to showcase a TCP/IP echo server application. This application runs on the Lightweight IP (lwIP) TCP/IP stack, an efficient solution for embedded systems.

Prerequisites

• Hardware:
  • Mimas AU-Plus FPGA Development Board
  • Cat 6 Ethernet Cable
  • USB C-type cable
  • 5V DC Power Supply
• Software:
  • AMD Vivado Design Suite 2025.1
  • Serial Terminal (PuTTY, Tera Term, etc.)

Let’s get Started

Step 1:

Download and install Vivado Board Support Package files for Mimas AU plus from here.

Step 2:

Start Vivado Design Suite, and select “Create Project” from Quick Start section. The project wizard will pop up.  Press next to proceed with creating the project.

Step 3:

Enter a name for the project and save it at a suitable location. Check the option “Create project subdirectory”. Click Next to continue.

Step 4:

In the Project Type window, select RTL Project and check the option “Do not specify sources at this time”. Click Next.

Step 5:

In the Default Part window, select “Mimas_AU_Plus_dev_VA0.0” from the Boards option. If not listed, make sure board support files are installed correctly. Click Next to continue.

Click Finish to complete creating a new project. A new project will be created by Vivado with the selected settings.

Step 6:

In the Flow Navigator panel, select Create Block Design under IP INTEGRATOR. Enter a name for the block design and click OK. An empty block design will be created.

Step 7:

Click the Board tab. The default peripherals available for the Mimas AU Plus board will be displayed.

Drag and drop DDR4, Fabric Fixed-Frequency Clock Oscillator, Reset and USB UART, into IPI Canvas.

Step 8:

Double click on Clocking Wizard IP block and change the settings as shown below. In the Output Clocks section, set:

• clk_out1 frequency to 100 MHz
• clk_out2 frequency to 333.333 MHz
• clk_out3 frequency to 125 MHz

Click OK to customize the IP.

Step 9:

Click Add IP, search for MicroBlaze, and Add it.

Click Run Block Automation with 64 KB of local memory and interrupt controller enabled.

Click Run Connection Automation and select all to connect AXI interfaces of DDR4, Uartlite IPs, and their clocks and resets.

Step 10:

Drag & Drop Gigabit Ethernet PHY interface into IPI Canvas.

Note: Click on the “Report IP Status” section under the “Reports” tab to review the status of all IPs. If the status indicates “design linking” for the Ethernet IP, it is necessary to download and incorporate the corresponding hardware evaluation license ([email protected]) to enable the proper functioning of the Ethernet IP.

Step 11:

Run Block Automation for AXI Ethernet and select “FIFO” for the AXI Streaming interface.

Step 12:

Click Run Connection Automation. Select the All Automation option and click OK.

Step 13:

Add AXI Timer into IPI Canvas and click Run Connection Automation.

Step 14:

Customize the Concat IP block as shown below.

Route the following connections to the inputs of the Concat block:

• interrupt on AXI Uartlite block
• interrupt on AXI Timer block
• interrupt on AXI-Stream FIFO
• interrupt and mac_irq on AXI 1G/2.5G Ethernet Subsystem

Make sure that the final design looks as shown above.

Step 15:

Select the Validate Design option from the Tools menu to ensure that connections are correct.

Step 16:

In the Sources window, right-click on the design and select Create HDL Wrapper. Click OK in the dialog box that appears.

Step 17:

Click Generate Bitstream under the PROGRAM AND DEBUG section of Vivado to synthesize, implement and generate the bitstream.

Step 18:

After generating the bitstream successfully, select Export -> Export Hardware from the File menu. Click Next.

Select the “include bitstream” checkbox and click Next.

Provide the XSA file name and save it at a suitable location. Click Next and click Finish in the next dialog box.

Step 19:

Launch Vitis IDE and create a new platform for the project, by selecting “Create Platform Component”,  click “Next”, in the Flow tab select the XSA file saved and finally click “Next” and “Finish” respectively.

Step 20:

Give the component name and the platform location and click on “Next”

Step 21:

In the next tab browse the XSA file , select it , click on “Next”. In the next OS and Processor tab click “Next” and “Finish”

After successful creation of the platform, build the platform.

Step 22:

After building the platform go to Board Support Packages configuration of the newly created platform and add lwip220 library to the platform.

Step 23:

After adding the lwip220 to the platform , click on the lwip to configure the lwip library.

For lwip_echo_server the following library config param values are expected:

lwip220_dhcp: True

lwip220_lwip_dhcp_does_acd_check: True

lwip220_pbuf_pool_size: 2048

xiltimer: XILTIMER_en_interval_timer: True

Initial Setup (DHCP)

Initially, configure the platform to use Dynamic Host Configuration Protocol (DHCP). This is essential for adding the application. Set the following parameters to True:

• lwip220_dhcp
• lwip220_lwip_dhcp_does_acd_check Once these parameters are set, you can add the lwIP echo server application to the platform.

Step 24:

Next create the lwip echo server Application component by selecting the “IwIp Echo Server” template from the “examples”.

In “Create Application Component” tab specify project name and location, click “Next”.

Select newly created Platform and click “Next”.

Select the domain as “Standalone_microblaze_0” and click “Next” and click on “Finish”.

When the lwip project is added successfully, build the project manually.

Static IP Configuration

After adding the application, if you want it to use a static IP address instead of DHCP, you must reconfigure the build. Set the following parameters to False:

• lwip220_dhcp
• lwip220_lwip_dhcp_does_acd_check
• lwip220_dhcp_options Finally, rebuild the application for the changes to take effect. This will allow the echo server to operate with a static IP.

Step 25:

Once the build is completed successfully, power up Mimas AU Plus FPGA Development Board using USB type C cable and connect the JTAG cable for programming the device.

Step 26:

Program the FPGA on Mimas AU Plus with a simple boot loop program by selecting the Program Device option from the Vitis menu.

Once the “Program Device” window opens give the path for .bit and .mmi files .

If the “BMM/MMI” File is not selected , manually browse and select the file .

Once the files are selected click on “Program” .

Step 27:

Meanwhile, open any serial terminal program (such as PuTTY, Teraterm etc) and open the port corresponding to Mimas AU Plus with a 9600 baud rate (the default baud rate given in UART IP). Program the board by selecting the “Run”.

Step 28:

Observe the details displayed on the serial terminal.

Step 29:

Connect the Ethernet cable to the board and the other end to the PC Ethernet port. Go to Control Panel.  Go to Network and Internet -> Network and Sharing Centre -> Change adapter settings.  Select “Change adapter settings”. Right-click on Ethernet, click properties, and select “IPv4”. Change the IPv4 address to 192.168.1.15 (any IP address can be used) and the default gateway to 192.168.1.1.

Step 30:

Open a telnet session with IP Address 192.168.1.10 (IP address as per main.c) at port 7, give input through the keyboard and observe the output. If you enter a character from the keyboard, you can observe the transmitted and echoed characters on telnet as shown.