Introduction:
Ethernet is a widely used protocol in the TCP/IP stack, enabling device communication in LANs. The TityraCore D200 FPGA, with its integrated ARM Cortex-A9 Processing System (PS) and programmable logic (PL), is an ideal platform for Ethernet-based applications. This design demonstrates an echo server application using the lightweight IP (lwIP) TCP/IP stack, where the server receives and echoes back TCP data.
The Zynq Processing System utilizes the Gigabit Ethernet MAC (GEM) to interface with an external PHY chip via the Reduced Gigabit Media-Independent Interface (RGMII). This setup highlights the seamless integration of hardware and software for high-speed Ethernet communication, making the TityraCore D200 FPGA a robust solution for networking applications.
Prerequisites:
Hardware:
- TityraCore D200 SODIMM Module.
- TityraCore SoC carrier.
- Cat 6 Ethernet Cable.
- Xilinx Platform Cable II JTAG debugger.
- USB Type C Cable.
Software:
- Xilinx Vivado Design Suite 2024.1
- Vitis classic 2024.1
- PUTTY Serial terminal.
Let’s get Started
The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with Zynq processing system using IP integrator. This article is written for Numato Lab’s Tityra core D200 Module, but can be adapted to any other Zynq based platform with minor changes. Screenshots are added wherever possible to make the process easier to the reader.
Step 1:
Download and install Vivado Board Support Package files for TityraCore D200 from here. Follow the readme in the link on how to install Vivado Board Support Package files for Numato Lab’s boards.
Step 2:
Start Vivado Design Suite, and select “Create New Project” from Quick Start section. The project wizard will pop up. Press next to proceed with creating the project.
Step 3:
Type in a project name and save it at a convenient location. For this example “Ethernet_echo” is used as project name, but feel free to use any name. Select the check box below to keep all project files in a single folder. The image below shows the settings for the example project. Click “Next” to continue.
Step 4:
Choose “RTL Project” as project type and check the option “Do not specify sources at this time”.
Step 5:
At the “Default Part” step, select “Boards” and choose Vendor as “numato.com”. Select “Tityra” and click “Next”. If Tityra is not displayed in the boards list, you will need to install Tityra board support files correctly.
Step 6:
Under Flow Navigator, select “Create Block Design” in IP Integrator. Give an appropriate name to design. We will call it “Ethernet” for example.
Step 7:
Go to Diagram window, right click and select “Add IP” from the popup menu. Search for ZYNQ7 Processing System. Add it to block design by double clicking.
Step 8:
Click on “Run Block Automation” option on the green bar.
Step 9:
In the “Run Block Automation” window, select the options as in image below and click OK.
Step 10:
Go to “Sources” tab, right click on “Ethernet” design file and select “Create HDL Wrapper”. Click OK on the window that appears to finish generating wrapper.
Step 11:
Click “Generate Bitstream” under PROGRAM AND DEBUG section and click “Yes” in any subsequent dialog window which comes up.
Step 12:
Once the bitstream is successfully generated, close any “Bitstream Generation Completed” dialog which comes up asking for what to do next.
Go to File -> Export -> Export Hardware…
Check “Include bitstream”, keep “Export to:” default, and click OK.
Step 13:
Launch Vitis classic.
Note: In Vivado 2024.1, accessing Vitis via the tools menu inadvertently launches Vitis Unified instead of Vitis Classic, which is our preferred tool for project creation. To utilize Vitis Classic, it is necessary to launch it separately.
Step 14:
In Vitis, IDE window select Create Application Project and click Next in the dialog box that appears.
In the Platform, window select Create a new platform from the hardware Tab and import the XSA file which is already created (Provide XSA file location). Click Next.
In the Application Project Details window, give an appropriate name for the Vitis Project and click Next. Click Next in the Domain window.
Select the lwIP Echo Server template from the list of available templates and click Finish.
Step 15:
Select Navigate to BSP Settings from Application Project Settings.
Select Board Support Package and click on Modify BSP Settings option.
In the Board Support Package Settings window, select lwip (Iwip220) library, change the dhcp_options to “false” and ensure that “debug options” are “false”.
Select phy_link_speed in temac_adapter_options as CONFIG_LINKSPEED1000.
After changing the library settings, click OK. vitis will update the BSP automatically. If that didn’t happen for any reason, run a build manually.
NOTE: Vitis does not include built-in support for KSZ Ethernet PHY drivers. To enable compatibility, the xemacpsif_physpeed file must be manually updated with the KSZ driver modifications. Replace the existing xemacpsif_physpeed file in your project with the provided file, which includes the necessary changes to support KSZ PHY drivers. This ensures proper Ethernet functionality in your application.
After modifying the xemacpsif_physpeed file Build the project.
Step 16:
Once the build is completed successfully, power up Tityra core D200 using an external DC power supply and connect the Xilinx Platform USB cable to the board.
Step 17:
Program the FPGA on TityraCore D200 by selecting the Program FPGA option from the Xilinx menu.
Step 18:
Open the COM port corresponding to TityraCore D200 in any serial terminal (PuTTY, Tera Term, etc.) with a 115200 baud rate. Now, right-click on the .elf file in Project Explorer and select “Launch on Hardware” as shown below.
Observe the details displayed on the serial terminal.
Step 19:
Connect the Ethernet cable to the board and the other end to the PC Ethernet port. Go to Control Panel. Go to Network and Internet -> Network and Sharing Centre -> Change adapter settings. Select “Change adapter settings”. Right-click on Ethernet, click properties, and select “IPv4”. Change the IPv4 address to 192.168.1.15 (any IP address can be used) and the default gateway to 192.168.1.1.
Step 20:
Open a telnet session with IP Address 192.168.1.10 (IP address as per main.c) at port 7, give input through the keyboard and observe the output. If you enter a character from the keyboard, you can observe the transmitted and echoed characters on telnet as shown.
