INTRODUCTION
Ethernet is a Link Layer Protocol in the TCP/IP protocol stack between the physical and data link layer. It is the most widely used protocol for Local Area Networks (LANs). Every device on Ethernet is assigned a unique MAC address for communication. Gigabit Ethernet refers to various technologies developed for transmitting Ethernet frames at the rate of gigabits per second. The Reduced Gigabit Media-Independent Interface (RGMII) is used to interface the Ethernet IP core on FPGA with the Gigabit Ethernet PHY chip on Elbert S7. The Media Access Layer converts the packets into a stream of data to be sent while the Physical Layer converts the stream of data into electrical signals. RGMII provides a media-independent interface so that MAC and PHY can be compatible, irrespective of the hardware used. In this tutorial, the Numato Lab Elbert S7 FPGA Development Board is used to demonstrate a TCP/IP echo server application. The echo server application runs on lightweight IP (lwIP) TCP/IP stack.
Prerequisites:
- Hardware:
- Elbert S7 FPGA Development Board
- Cat 6 Ethernet Cable
- AMD Platform Cable USB II JTAG (optional)
- USB Type C cable
- 5V-12V DC Power Supply
- Software:
- AMD Vivado Design Suite 2024.1
- Telnet Application
- Serial Terminal (PuTTY, Tera Term, etc.)
Let’s get started
Step 1:
Launch Vivado Design Suite, and go to “File->Project->New” to create a new project. The “New project” wizard will pop up. Click “Next” to continue.
Step 2:
Enter a name for the project and save it at a suitable location. Check the option “Create project subdirectory”. Click Next to continue.
Step 3:
In the “Project type” wizard, select “RTL Project” and select the checkbox to skip specifying the source at the moment. Click “Next“.
Step 4:
At the “Default Part” wizard, select “Boards” and then select the “Elbert_S7” board. Click “Next” to continue. If Elbert is not displayed in the Boards list, you need to install Elbert board support files appropriately and retry this step. You can download Elbert board support files for Vivado here. Follow the readme in the link on how to install the Vivado board files in your system.
In the next wizard, click “Finish” to create a new project. When the new project wizard exits, a new project will open up in Vivado with the selected settings.
Step 5:
In the Flow Navigator panel, select Create Block Design under IP INTEGRATOR. Enter a name for the block design and click OK. An empty block design will be created
Step 6:
Go to Diagram window, right click and select “Add IP” from the popup menu. Search for “MicroBlaze” and add it to the design by double-clicking it.
Click “Run Block Automation” present in the “Designer Assistance available” bar on the top left corner of the window to complete the design. Select the settings as shown in the following image. Click “OK” for Vivado to automatically configure the blocks for you.
Step 7:
Double click “Clocking Wizard” IP and customize “Board” settings as shown in the following image.
Click OK to customize the IP.
Step 8:
Click the Board tab. The default peripherals available for the Elbert S7 board will be displayed.
Drag and drop DDR3 SDRAM, USB UART, and Gigabit Ethernet PHY into IPI Canvas.
Ensure that sys_clk_i of Memory Interface Generator is connected to clk_out2.
Step 9:
Click Run Connection Automation and select all .
Step 10:
Run Block Automation
-
for AXI Ethernet and select “DMA/FIFO” for the AXI Streaming interface.
-
for Microblaze_0 select “Keep Classic MicroBlaze” option and click “OK“
Step 11:
Click Run Connection Automation. Select the All Automation option and click OK.
Step 12:
Add AXI Timer into IPI Canvas and click Run Connection Automation.
Step 13:
Customize the Concat IP block as shown below.
Route the following connections to the inputs of the Concat block:
- interrupt on AXI Uartlite block
- interrupt on AXI Timer block
- interrupt on AXI-Stream FIFO
- interrupt and mac_irq on AXI 1G/2.5G Ethernet Subsystem
Make sure that the final design looks as shown above.
Step 14:
Select the Validate Design option from the Tools menu to ensure that connections are correct.
Step 15:
In the Sources window, right-click on the design and select Create HDL Wrapper. Click OK in the dialog box that appears.
Step 16:
Click Generate Bitstream under the PROGRAM AND DEBUG section of Vivado to synthesize, implement and generate the bitstream.
Step 17:
After generating the bitstream successfully, select Export -> Export Hardware from the File menu. Click Next.
Select the “include bitstream” checkbox and click Next.
Provide the XSA file name and save it at a suitable location. Click Next and click Finish in the next dialog box.
Step 18:
Launch Vitis classic.
Note: In Vivado 2024.1, accessing Vitis via the tools menu inadvertently launches Vitis Unified instead of Vitis Classic, which is our preferred tool for project creation. To utilize Vitis Classic, it is necessary to launch it separately.
Step 19:
In Vitis, IDE window select Create Application Project and click Next in the dialog box that appears.
In the Platform, window select Create a new platform from the hardware Tab and import the XSA file which is already created (Provide XSA file location). Click Next.
In the Application Project Details window, give an appropriate name for the Vitis Project and click Next. Click Next in the Domain window.
Select the lwIP Echo Server template from the list of available templates and click Finish.
Step 20:
Select Navigate to BSP Settings from Application Project Settings.
Select Board Support Package and click on Modify BSP Settings option.
In the Board Support Package Settings window, select lwip (Iwip220) library, change the dhcp_options to “false” and ensure that “debug options” are “false”.
Select phy_link_speed in temac_adapter_options as CONFIG_LINKSPEED1000.
After changing the library settings, click OK. vitis will update the BSP automatically. If that didn’t happen for any reason, run a build manually.
NOTE: Vitis does not include built-in support for KSZ Ethernet PHY drivers. To enable compatibility, the xaxiemacif_physpeed file must be manually updated with the KSZ driver modifications. Replace the existing xaxiemacif_physpeedfile in your project with the provided file, which includes the necessary changes to support KSZ PHY drivers. This ensures proper Ethernet functionality in your application.
After modifying the xaxiemacif_physpeed file Build the project.
Step 21:
Once the build is completed successfully, power up Elbert S7 using USB type C.
Step 22:
Program the FPGA on Elbert S7 by selecting the Program Device option from the vitis menu.
Step 23:
Open the COM port corresponding to Elbert S7 in any serial terminal (PuTTY, Tera Term, etc.) with a 9600 baud rate. Now, right-click on the .elf file in Project Explorer and select “Launch on Hardware” as shown below.
Observe the details displayed on the serial terminal.
Step 24:
Connect the Ethernet cable to the board and the other end to the PC Ethernet port. Go to Control Panel. Go to Network and Internet -> Network and Sharing Centre -> Change adapter settings. Select “Change adapter settings”. Right-click on Ethernet, click properties, and select “IPv4”. Change the IPv4 address to 192.168.1.15 (any IP address can be used) and the default gateway to 192.168.1.1.
Step 25:
Open a telnet session with IP Address 192.168.1.10 (IP address as per main.c) at port 7, give input through the keyboard and observe the output. If you enter a character from the keyboard, you can observe the transmitted and echoed characters on telnet as shown.
