Introduction
Vivado Design Suite by Xilinx is used for synthesis and analysis of HDL designs with additional features for SoC development and high-level synthesis. Xilinx recommends use of Vivado Design Suite for new designs with Ultrascale, Virtex-7, Kintex-7, Artix-7, and Zynq-7000. In this article we will use Vivado to create a basic “Hello World” program for TityraCore Z7 SODIMM Module running on Zynq’s ARM processor.
Prerequisites
To follow this article, you would need the following:
- Hardware:
- TityraCore Z7 SODIMM module
- TityraCore SoC carrier
- Xilinx Platform Cable II JTAG debugger
- USB Type C cable.
- 5-12V DC Power Supply.
- Software:
- Xilinx Vivado Design Suite 2024.1
- Vitis Classic 2024.1
- FT_Prog tool for configuring on-board FT2232H USB Serial converter (download and install from FTDI website)
Let’s get started
The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with Zynq processing system using IP integrator. This article is written for Numato Lab’s TityraCore Z7 SODIMM module, but can be adapted to any other Zynq based platform with minor changes. Screenshots are added wherever possible to make the process easier to the reader.
Step 1:
Download and install Vivado Board Support Package files for Tityra from here. Follow the readme in the link on how to install Vivado Board Support Package files for Numato Lab’s boards.
Step 2:
Start Vivado Design Suite, and select “Create New Project” from Quick Start section. The project wizard will pop up. Press next to proceed with creating the project.
Step 3:
Type in a project name and save it at a convenient location. For this example “Tityra_hello” is used as project name, but feel free to use any name. Select the check box below to keep all project files in a single folder. The image below shows the settings for the example project. Click “Next” to continue.
Step 4:
Choose “RTL Project” as project type and check the option “Do not specify sources at this time”.
Step 5:
At the “Default Part” step, select “Boards” and choose Vendor as “numato.com”. Select “Tityra” and click “Next”. If TityraCore is not displayed in the boards list, you will need to install Tityra board support files correctly.
Continue the wizard and finish creating the project. When the new project wizard exits, a new project will be opened up in Vivado with the settings you have selected.
Step 6:
Under Flow Navigator, select “Create Block Design” in IP Integrator. Give an appropriate name to design. We will call it “Tityra” for example.
Step 7:
Go to Diagram window, right click and select “Add IP” from the popup menu. Search for ZYNQ7 Processing System. Add it to block design by double clicking.
Step 8:
Click on “Run Block Automation” option on the green bar.
Step 9:
In the “Run Block Automation” window, select the options as in image below and click OK.
Step 10:
Go to “Sources” tab, right click on “tityra” design file and select “Create HDL Wrapper”. Click OK on the window that appears to finish generating wrapper.
Step 11:
Click “Generate Bitstream” under PROGRAM AND DEBUG section and click “Yes” in any subsequent dialog window which comes up.
Step 12:
Once the bitstream is successfully generated, close any “Bitstream Generation Completed” dialog which comes up asking for what to do next.
Step 13:
Go to File -> Export -> Export Hardware…
Check “Include bitstream”, keep “Export to:” default, and click OK.
Step 14:
Launch Vitis classic.
Note: In Vivado 2024.1, accessing Vitis via the tools menu inadvertently launches Vitis Unified instead of Vitis Classic, which is our preferred tool for project creation. To utilize Vitis Classic, it is necessary to launch it separately.
After opening Vitis Classic, choose a folder for keeping all the Vitis project files in the single folder.
After Vitis windows opens, click on “Create Application Project” and click “next” on the subsequent window.
Step 15:
To create a new platform for the project, select “create a new platform from hardware (XSA)” and select the XSA file saved using the step 14. Type in a project name, leave other options as default and click “Next”. In the next window, select Hello World template and click “Finish”.
Step 16:
Once the project is created build the project manually.
Once the build is complete successfully, power up TityraCore Z7 SODIMM Module using carrier and connect Xilinx Platform USB and USB type C cable for Serial debugging to the board. Make sure to change the TityraCore’s Boot Mode to JTAG. Please refer to user manual to learn more about configuring Tityra’s Boot Mode.
Step 17:
Program the board by selecting Vitis -> Program Device -> okay. Click Program in the window that opens up.
Step 18:
Open any serial terminal program (such as PuTTY, Teraterm etc) and open the port corresponding to TityraCore’s Channel B at 115200 baudrate.
Step 19:
After FPGA is successfully programmed, right click on the executable .elf file of our Hello World program, go to Run As -> 1 Launch on Hardware (Single Application Debug), as shown in image below:
If everything went well, the application running on the board should print “Hello World” over the UART and should be displayed on the Serial Terminal application.
