EagleCore ZU-Plus MPSoC

Introduction

DDR memory is one of the key components in any Zynq MPSoC design, as it is directly used by the Processing System (PS) for running applications, storing data, and handling high-speed operations. Verifying that the DDR is working correctly is an important step before moving on to complex designs. In the Zynq UltraScale+ MPSoC, the DDR controller is integrated into the PS, making it easier to test and validate memory functionality. In this article, we will demonstrate how to perform a basic DDR test in the PS section to ensure reliable operation.

Prerequisites

To follow this article, you would need the following:

• Hardware:
  1. EagleCore ZU-Plus MPSoC SOM.
  2. EagleCore ZU01 Carrier.
  3. AMD Platform Cable II JTAG debugger.
  4. USB Type C Cable.
  5. 12V DC Power Supply.
• Software:
  1. AMD Vivado Design Suite 2025.1
  2. Vitis 2025.1

Let’s get started

The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with Zynq processing system using IP integrator. This article is written for Numato Lab’s TityraCore D200, but can be adapted to any other Zynq based platform with minor changes. Screenshots are added wherever possible to make the process easier to the reader.

Step 1:

Download and install Vivado Board Support Package files for EagleCore ZU-Plus MPSoC SOM from here. Follow the readme in the link on how to install Vivado Board Support Package files for Numato Lab’s boards.

Step 2:

Start Vivado Design Suite, and select “Create Project” from Quick Start section. The project wizard will pop up.  Press “next” to proceed with creating the project.

 

Step 3:

Type in a project name and save it at a convenient location. For this example “DDR4” is used as project name, but feel free to use any name. Select the check box below to keep all project files in a single folder. The image below shows the settings for the example project. Click “Next” to continue.

Step 4:

Choose “RTL Project” as project type and check the option “Do not specify sources at this time”.

Step 5:

At the “Default Part” step, select “Boards” and choose Vendor as “numato.com”. Select “Eaglecore ZU-Plus development kit” and click “Next”. If Eaglecore ZU-Plus development kit is not displayed in the boards list, you will need to install Eaglecore ZU-Plus development kit board support files correctly.

 

Step 6:

Under Flow Navigator, select “Create Block Design” in IP Integrator. Give an appropriate name to design. We will call it “Eaglecore_zu” for example.

Step 7:

Go to Diagram window, right click and select “Add IP” from the popup menu. Search for Zynq UltraScale+ MPSoC. Add it to block design by double clicking.

Step 8:

Click on “Run Block Automation” option on the green bar.

Step 9:

In the “Run Block Automation” window, select the options as in image below and click OK.

 

Step 10:

Go to “Sources” tab, right click on “Eaglecore_zu” design file and select “Create HDL Wrapper”. Click OK on the window that appears to finish generating wrapper.

 

Step 11:

Click “Generate Bitstream” under PROGRAM AND DEBUG section and click “Yes” in any subsequent dialog window which comes up.

Step 12:

Once the bitstream is successfully generated, close any “Bitstream Generation Completed” dialog which comes up asking for what to do next.

Go to File -> Export -> Export Hardware…

Check “Include bitstream”, keep “Export to:” default, and click OK.

 

 

Step 13:

Select Launch Vitis IDE from the Tools menu.

Step 14:

After Vitis Unified IDE window opens, click on “Open Workspace” and select necessary folder to keep the Vitis files.

 

Step 15:

Create a new platform for the project, by selecting “Create Platform Component”,  click “Next”, in the Flow tab select the XSA file saved using the step 12 and finally click “Next” and “Finish” respectively.

After successful creation of the platform, build the platform.

Step 16:

Next create the DDR4_test Application component by selecting the “Memory tests” template from the “examples”,

In “Create Application Component” tab specify project name and location, click “Next”

Select newly created Platform and click “Next”.

When the Memory tests project is added successfully, build the project manually.

Step 17:

Once the build is completed sucessfully, power up the EagleCore ZU module using an external 12V DC power supply. Then, connect a Type-C cable to program the board (Note: ensure that PGM SEL is set to USB programming).

Step 18:

Program the FPGA on EagleCore ZU with a simple boot loop program by selecting the Program Device option from the Vitis menu.

Once the “Program Device” window opens click on “Program“.

Step 19:

Meanwhile, open any serial terminal program (such as PuTTY, Teraterm etc) and open the port corresponding to Eaglecore ZU with a 115200baud rate (the default baud rate given in UART IP).  Program the board by selecting the “Run”.

Step 20:

If everything went well, the application running on the board should print the memory testing Process over the UART and should be displayed on the Serial Terminal application.