DDR3 DRAM Test On TityraCore D200

Introduction

Testing DDR3 DRAM on an FPGA involves checking the performance and reliability of dynamic random-access memory (DRAM) modules within a FPGA. This process ensures that the DRAM interacts correctly with the FPGA, verifying that data is stored and retrieved accurately under various conditions. Effective testing is crucial for optimizing memory systems and enhancing overall system performance. The Purpose of this article is to help readers to understand how to test DRAM memory available on tityra using Zynq DRAM tests template.

Prerequisites:

For following this article, you would require:

Hardware:
- TityraCore Z7 SODIMM FPGA
- TityraCore Z7 carrier board
- Xilinx Platform Cable JTAG debugger
- USB type C cable
Software:
1. Xilinx Vivado and Vitis 2024.1

Let’s get started

The following steps will walk you through the process of creating a new project with Vivado and building a hardware platform with Zynq processing system using IP integrator. This article is written for Numato Lab’s TityraCore D200, but can be adapted to any other Zynq based platform with minor changes. Screenshots are added wherever possible to make the process easier to the reader.

Step 1:

Download and install Vivado Board Support Package files for Tityra from here. Follow the readme in the link on how to install Vivado Board Support Package files for Numato Lab’s boards.

Step 2:

Start Vivado Design Suite, and select “Create Project” from Quick Start section. The project wizard will pop up. Press “next” to proceed with creating the project.

Step 3:

Type in a project name and save it at a convenient location. For this example “DDR3_eye_test” is used as project name, but feel free to use any name. Select the check box below to keep all project files in a single folder. The image below shows the settings for the example project. Click “Next” to continue.

Step 4:

Choose “RTL Project” as project type and check the option “Do not specify sources at this time”.

Step 5:

At the “Default Part” step, select “Boards” and choose Vendor as “numato.com”. Select “Tityra” and click “Next”. If tityra is not displayed in the boards list, you will need to install tityra board support files correctly.

Step 6:

Under Flow Navigator, select “Create Block Design” in IP Integrator. Give an appropriate name to design. We will call it “DDR3_eye” for example.

Step 7:

Go to Diagram window, right click and select “Add IP” from the popup menu. Search for ZYNQ7 Processing System. Add it to block design by double clicking.

Step 8:

Select “Run Block Automation” in the above right corner of the window and select “ok” in the upcoming window. To assign IIC_1 as external, right-click on it and choose the “Make External” option. The resulting image of the IP will resemble the following.

Step 9:

Now we have to add constraints for the external IIC_1 port. In the “Project Manager”, select “Add sources” and select “add or create constraints”. Select “create file” and give necessary name for constraint file. Here we are using the name “DDR3_eye”, feel free to use any name.

Double-click the XDC file to open it, then paste the following constraint set.

set_property PACKAGE_PIN W18 [get_ports IIC_1_0_scl_io]
set_property PACKAGE_PIN W16 [get_ports IIC_1_0_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_1_0_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_1_0_sda_io]

Step 10:

Go to “Sources” tab, right click on “DDR3_eye” design file and select “Create HDL Wrapper”. Click OK on the window that appears to finish generating wrapper.

Step 11:

Click “Generate Bitstream” under PROGRAM AND DEBUG section and click “Yes” in any subsequent dialog window which comes up.

Step 12:

Once the bitstream is successfully generated, close any “Bitstream Generation Completed” dialog which comes up asking for what to do next.

Go to File -> Export -> Export Hardware…

Check “Include bitstream”, keep “Export to:” default, and click OK.

Provide the XSA file name and save it at a suitable location. Click Next and click Finish in the next dialog box.

Step 13:

Launch Vitis classic.

Note: In Vivado 2024.1, accessing Vitis via the tools menu inadvertently launches Vitis Unified instead of Vitis Classic, which is our preferred tool for project creation. To utilize Vitis Classic, it is necessary to launch it separately. This differentiation is applicable exclusively to versions released from 2023.2 onwards.

Step 14:

In Vitis, IDE window select Create Application Project and click Next in the dialog box that appears.

In the Platform window select Create a new platform from the hardware Tab and import the XSA file which is already created (Provide XSA file location). Click Next.

In the Application Project Details window, give an appropriate name for the Vitis Project and click Next. Click Next in the Domain window.

Select the Zynq DRAM tests template from the list of available templates and click Finish.

Step 15:

Once the project is created build the project manually.

Once the build is complete successfully, power up TityraCore Z7 SODIMM module using carrier and connect Xilinx Platform USB cable and USB type C cable for Serial debugging to the board. Make sure to change the TityraCore’s Boot Mode to JTAG. Please refer to user manual to learn more about configuring Tityra’s Boot Mode.

Step 16:

Program the board by selecting Vitis -> Program Device -> okay. Click Program in the window that opens up.

Step 17:

Open any serial terminal program (such as PuTTY, Teraterm etc) and open the port corresponding to TityraCore’s Channel B at 115200 baudrate.

Step 18:

After FPGA is successfully programmed, right click on the executable .elf file of our Zynq DRAM test program, go to Run As -> 1 Launch on Hardware (Single Application Debug), as shown in image below:

If everything went well, you will see the below output on the Serial Terminal application.

TityraCore Z7 SODIMM FPGA