Xilinx Spartan 7 FPGA Boards

Narvi Spartan 7 FPGA Module

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Introduction

Narvi - Spartan 7 FPGA Module

Narvi is an easy to use FPGA Development board featuring Spartan 7 FPGA (XC7S50 – CSG324A package) with FTDI’s FT2232H Dual-Channel USB device. It is specially designed for the development and integration of FPGA based accelerated features to other designs. The Narvi – Spartan 7 FPGA Board is pin compatible with Saturn Spartan 6 FPGA ModuleSkoll Kintex 7 FPGA ModuleNeso Artix 7 FPGA ModuleStyx Zynq 7020 FPGA Module and Telesto MAX10 FPGA Module and thus offers a seamless upgrade path. The high-speed USB 2.0 interface provides fast and easy configuration download to the onboard SPI flash. No programmer or special downloader cable is needed to download the bit stream to the board. The second FTDI channel can be used to develop custom high data-rate USB based applications. Narvi provides user flexibility in adding their own peripherals through IO Expansion Headers.

Board Features

  • Pin compatible with Saturn Spartan 6 FPGA Module, Skoll Kintex 7 FPGA ModuleNeso Artix 7 FPGA Module, Styx Zynq 7020 FPGA Module and Telesto MAX10 FPGA Module and offers a seamless upgrade path
  • FPGA: XC7S50 in CSGA324 package, Speed Grade: -1
  • DDR3: 2Gb DDR3 (MT41J128M16HA-125:K or equivalent)
  • Flash memory: 128 Mb Quadbit SPI flash memory (N25Q128A13ESE40E)
  • 100MHz CMOS oscillator
  • High-Speed USB 2.0 interface for On-board flash programming. FT2232H Channel B is dedicated for SPI Flash /JTAG Programming. Channel A can be used for custom applications.
  • Onboard voltage regulators for single power rail operation
  • FPGA configuration via JTAG and USB
  • Maximum IOs for user-defined purposes
    • FPGA – 130 IOs
    • FT2232H – 8 IOs

Applications

  • Product Prototype Development
  • Accelerated computing integration
  • Development and testing of custom embedded processors
  • Signal Processing
  • Communication devices development
  • Educational tool for Schools and Universities

How to use Narvi Spartan 7 FPGA Module

The following sections describe in detail how to use this module.

Hardware Accessories Required

For easy and fast installation, you may need the following items along with the Narvi module.

  • USB A to Micro B cable
  • DC Power supply
  • A Xilinx Platform Cable USB II compatible JTAG programmer (optional)

Connection Diagram

The following connection diagram should be used for reference only. The schematics are available at the end of this document for detailed information.

USB Interface

The onboard high speed USB controller helps a PC/Linux/Mac computer to communicate with this module. Use a USB A to Micro B cable to connect with a PC. By default, the module is powered by USB so make sure not to overcrowd unpowered USB hubs (the picture on the right shows Micro B connector).

DC Power Supply

The board is configured to use power from DC power supply by connecting it to the External DC Jack. Please refer to the marking on the board for more details. The external power supply should be in the range of +7 to +12V, with sufficient current rating.

JTAG Connector

JTAG connector allows the FPGA’s JTAG registers to be accessed using a JTAG cable, compatible with Xilinx Platform Cable USB. Use this header, to attach JTAG cable for programming and debugging.

Reset Button and LED

Narvi S7 features a Push-button S2 normally meant to be used as “Reset” signal for designs running on FPGA. Push-button S2 is connected to FPGA pin T14. Push-button S2 is active-high. This push button can also be used for any other input and is not just limited to be used as a Reset signal.

Narvi S7 also features a general purpose LED D6 which can be used in the RTL design as per requirement. LED D6 is connected to FPGA pin G13. LED D6 is active-low.

PROG_B Button

Narvi features a Push-button S1 normally meant to be used as “PROG_B” signal for configuration reset. Push-button S1 is connected to FPGA pin R8. For enabling manual configuration reset, push-button S1 is connected to GND. The user can reconfigure the FPGA manually, by pressing this push-button S1.

“PROG_B” is active-low input pin (pulled up with 4.7K external resistor) to the FPGA and it controls the configuration logic. An assertion followed by de-assertion cycle on PROG_B pin resets the FPGA and initializes the new configuration.

JTAG/SPI Configuration on FT2232H Channel B

Channel B of FT2232H can be connected to the SPI bus that connects the SPI Flash chip to the FPGA or to the JTAG pins of the FPGA. When FT2232H channel B is connected to FPGA JTAG, the JTAG signals can be accessed directly through FT2232H. This is the default configuration set when Narvi S7  is shipped.

Please see the tables below for information about selecting SPI or JTAG for FT2232H channel B.

Solder Jumpers P2

Jumper Configuration for SPIJumper Configuration for JTAG
1 - 2 (S1)1 - 3 (J1)
5 - 6 (S2)4 - 6 (J2)

Solder Jumpers P3

Jumper Configuration for SPIJumper Configuration for JTAG
1 - 2 (S3)1 - 3 (J3)
5 - 6 (S4)4 - 6 (J4)

By default, Narvi S7 ships with the solder jumpers in JTAG configuration. During normal usage, users should not change these jumpers from their factory default configuration.

GPIOs

This device is equipped with a maximum 130 user IO pins that can be used for various custom applications. All user IOs are length matched and can be used as differential pairs.

Header P4

Pin No. On The HeaderGPIO Pin Name Spartan-7 (CSGA324) Pin No.Pin No. On The HeaderGPIO Pin Name Spartan-7 (CSGA324) Pin No.Pin No. On The HeaderGPIO Pin Name Spartan-7 (CSGA324) Pin No.Pin No. On The HeaderGPIO Pin Name Spartan-7 (CSGA324) Pin No.
A1GNDB1VCC3V3C1VIND1GND
A2GPIO_1_NA14B2GPIO_1_PB14C2GPIO_4_NA16D2GPIO_4_PB16
A3GPIO_28_NA9B3GPIO_28_PA10C3GPIO_3_NA15D3GPIO_3_PB15
A4GPIO_5_NA17B4GPIO_5_PB17C4GPIO_25_NA11D4GPIO_25_PB11
A5GPIO_21_NC14B5GPIO_21_PC13C5GPIO_20_NA13D5GPIO_20_PB13
A6GPIO_23_ND12B6GPIO_23_PE12C6GPIO_33_NG6D6GPIO_33_PH6
A7GPIO_14_ND6B7GPIO_14_PE6C7GPIO_26_NF5D7GPIO_26_PG5
A8GPIO_8_NA4B8GPIO_8_PA5C8GPIO_12_NC7D8GPIO_12_PD7
A9GPIO_15_ND5B9GPIO_15_PE5C9GPIO_13_NA6D9GPIO_13_PB7
A10GPIO_7_NB5B10GPIO_7_PC5C10NCD10NC
A11NCB11NCC11GPIO_6_NA7D11GPIO_6_PA8
A12NCB12NCC12GPIO_18_NE4D12GPIO_18_PF4
A13GNDB13GNDC13GNDD13GND
A14NCB14NCC14GPIO_19_NA2D14GPIO_19_PA3
A15GPIO_2_NB2B15GPIO_2_PC2C15GPIO_27_NF1D15GPIO_27_PF2
A16GPIO_11_ND1B16GPIO_11_PE1C16GPIO_10_NB1D16GPIO_10_PC1
A17NCB17NCC17NCD17NC
A18GPIO_16_NB4B18GPIO_16_PC4C18GPIO_17_NB3D18GPIO_17_PC3
A19NCB19NCC19GPIO_30_NG1D19GPIO_30_PG2
A20GPIO_22_ND2B20GPIO_22_PE2C20GPIO_24_NE3D20GPIO_24_PF3
A21GPIO_31_NH4B21GPIO_31_PH5C21GPIO_32_NJ1D21GPIO_32_PJ2
A22GPIO_29_NH2B22GPIO_29_PH3C22GPIO_9_NJ3D22GPIO_9_PJ4
A23GNDB23GNDC23GNDD23GND
A24VCC3V3B24VCC3V3C24VCC3V3D24VCC3V3

Header P5

Pin No. On The HeaderGPIO Pin NameSpartan-7 (CSGA324) Pin No.Pin No. On The HeaderGPIO Pin NameSpartan-7 (CSGA324) Pin No.Pin No. On The HeaderGPIO Pin NameSpartan-7 (CSGA324) Pin No.Pin No. On The HeaderGPIO Pin NameSpartan-7 (CSGA324) Pin No.
A1BCBUS0*B1BCBUS1C1VCC3V3D1GND
A2BCBUS2B2BCBUS3C2GPIO_46_PC17D2GPIO_46_NB18
A3BCBUS4B3BCBUS5C3GPIO_47_PD16D3GPIO_47_ND17
A4BCBUS6B4BCBUS7C4GPIO_49_PF18D4GPIO_49_NE18
A5GPIO_37_PD18B5GPIO_37_NC18C5GPIO_54_PC12D5GPIO_54_NC11
A6GPIO_35_PG16B6GPIO_35_NG17C6GPIO_43_PN15D6GPIO_43_NP16
A7GPIO_36_PE14B7GPIO_36_NE15C7GPIO_44_PH18D7GPIO_44_NG18
A8GPIO_34_PF14B8GPIO_34_NF15C8GPIO_48_PE16D8GPIO_48_NE17
A9GPIO_50_PH16B9GPIO_50_NH17C9GPIO_41_PJ13D9GPIO_41_NJ14
A10GPIO_51_PK14B10GPIO_51_NJ15C10GPIO_40_PK16D10GPIO_40_NJ16
A11GPIO_52_PR15B11GPIO_52_NT15C11GPIO_39_PH15D11GPIO_39_NG15
A12GNDB12GNDC12GNDD12GND
A13GNDB13GNDC13GNDD13GND
A14GPIO_64_PU16B14GPIO_64_NV17C14GPIO_61_PU17D14GPIO_61_NU18
A15GPIO_42_PR16B15GPIO_42_NR17C15GPIO_45_PH13D15GPIO_45_NH14
A16GPIO_62_PP14B16GPIO_62_NP15C16GPIO_53_PC10D16GPIO_53_NC9
A17GPIO_63_PU15B17GPIO_63_NV16C17GPIO_57_PT12D17GPIO_57_NT13
A18GPIO_56_PU12B18GPIO_56_NV13C18GPIO_38_PF13D18GPIO_38_NE13
A19GPIO_59_PU11B19GPIO_59_NV12C19GPIO_55_PV14D19GPIO_55_NV15
A20GPIO_58_PR11B20GPIO_58_NT11C20V_PJ10D20V_NK9
A21GPIO_60_PP13B21GPIO_60_NR13C21TCKD9D21TDOT8
A22GPIO_65_PM14B22GPIO_65_NN14C22TDIR9D22TMST9
A23INIT_BU8B23VCC3V3C23PROGRAM_BR8D23VCC3V3
A24GNDB24GNDC24GNDD24GND

* BCBUS0 – BCBUS7 are pins of FTDI FT2232H Dual-Channel USB device.

FT2232H - Spartan-7 (CSGA324) FPGA Connection Details

FTDI Pin No.Pin Function (245 FIFO)Spartan 7 (CSGA324) Pin No.
16FTDI-D0L13
17FTDI-D1N13
18FTDI-D2L17
19FTDI-D3L18
21FTDI-D4M17
22FTDI-D5M18
23FTDI-D6M16
24FTDI-D7N18
26FTDI-RXF#P18
27FTDI-TXE#P17
28FTDI-RD#R18
29FTDI-WR#T18
30FTDI-SIWUAL16
32FTDI-CLKOUTR14
33FTDI-OE#R12

Driver Installation

Windows

This product requires a driver to be installed for proper functioning when used with Windows. The Numato Lab Narvi S7 driver can be downloaded from here. When driver installation is complete, the module should appear in Tenagra FPGA System Management Software as Narvi Spartan 7 FPGA Module.

Linux

The Linux ships with the drivers required for Narvi S7. It should be enough to run the following two commands in the terminal:

>> sudo modprobe ftdi_sio
>> echo 2a19 100D > /sys/bus/usb-serial/drivers/ftdi_sio/new_id

Generating Bitstream Using Vivado

The bitstream can be generated for Narvi in Vivado by following the steps below:

Step 1: It is recommended to generate .bin bitstream file along with .bit bitstream file. Click “Bitstream Settings”.

Step 2: Select “-bin_file*” option in the dialog window and Click OK.

Step 3: Finally click “Generate Bitstream”.

Programming Narvi Using JTAG

Narvi Spartan 7 FPGA Module features an onboard JTAG connector which facilitates easy reprogramming of SRAM and onboard SPI flash through JTAG programmer like “Xilinx Platform cable USB”. Following steps illustrate how to program FPGA on Narvi using JTAG.

Step 1: By using JTAG cable, connect Xilinx platform cable USB to Narvi and power it up.

Step 2: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 3: If the device is detected successfully, then select “Program Device” after right clicking on the target device “xc7s50_0 (1)” as shown below.

Step 4: In the dialog window which opens up, Vivado automatically chooses correct bitstream file if the design was synthesized, implemented and bitstream generated successfully. If needed, browse to the bitstream which needs to be programmed to FPGA. Finally, click “Program”.

As soon as “Program” is clicked, a green colored DONE LED (D1) on Narvi should light up, indicating that programming process is going on. This LED will turn off when the configuration is complete.

Programming QSPI Flash using Vivado

A .bin or .mcs file is required for programming Narvi’s onboard QSPI flash.

Step 1: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 2: If the device is detected successfully, then select “Add Configuration Memory Device” after right clicking on the target device “xc7s50_0” as shown below.

Step 3: Select the memory device “mt25ql128-spi-x1_x2_x4 (which is equivalent to n25q128-3.3v-spi-x1_x2_x4)”, then click OK.

Step 4: After completion of Step 3 the following dialog box will open. Click OK.

Step 5: Browse to the working .bin file or the .mcs file (whichever applicable) and click OK to program as shown below. If programming is successful, a confirmation message will be displayed.

Programming Narvi Using Tenagra

For steps on how to program Narvi using Tenagra, refer the Getting started with Tenagra FPGA System Management Software article.

Technical Specifications

Parameter *ValueUnit
Basic Specifications
Number of GPIOs130
On-board oscillator frequency (ASEM1-100.000MHZ-LC-T)100MHz
DDR3 SDRAM (MT41J128M16HA - 125 or Equivalent)2Gb
Quad SPI Flash Memory (N25Q128A13ESE40E)128Mb
Power supply voltage (USB or External)5 - 12V
FPGA Specifications
Internal supply voltage relative to GND -0.5 to 1.1 V
Auxiliary supply voltage relative to GND -0.5 to 2.0V
Output drivers supply voltage relative to GND -0.5 to 3.6V

Mechanical Dimensions

Vivado XDC Constraints

Schematics

Narvi GPIO Trace Length Details

Narvi GPIO Easy Reference

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