Xilinx Spartan 7 FPGA Boards

Narvi Spartan 7 FPGA Module

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Narvi - Spartan 7 FPGA Module

Narvi is an easy to use FPGA Development board featuring Spartan 7 FPGA (XC7S50 – CSG324A package) with FTDI’s FT2232H Dual-Channel USB device. It is specially designed for the development and integration of FPGA based accelerated features to other designs. The Narvi – Spartan 7 FPGA Board is pin compatible with Saturn Spartan 6 FPGA ModuleSkoll Kintex 7 FPGA ModuleNeso Artix 7 FPGA ModuleStyx Zynq 7020 FPGA Module and Telesto MAX10 FPGA Module and thus offers a seamless upgrade path. The high-speed USB 2.0 interface provides fast and easy configuration download to the onboard SPI flash. No programmer or special downloader cable is needed to download the bit stream to the board. The second FTDI channel can be used to develop custom high data-rate USB based applications. Narvi provides user flexibility in adding their own peripherals through IO Expansion Headers.

Board Features

  • Pin compatible with Saturn Spartan 6 FPGA Module, Skoll Kintex 7 FPGA ModuleNeso Artix 7 FPGA Module, Styx Zynq 7020 FPGA Module and Telesto MAX10 FPGA Module and offers a seamless upgrade path
  • FPGA: XC7S50 in CSGA324 package, Speed Grade: -1
  • DDR3: 2Gb DDR3 (MT41J128M16HA-125:K or equivalent)
  • Flash memory: 128 Mb Quadbit SPI flash memory (N25Q128A13ESE40E)
  • 100MHz CMOS oscillator
  • High-Speed USB 2.0 interface for On-board flash programming. FT2232H Channel B is dedicated for SPI Flash /JTAG Programming. Channel A can be used for custom applications.
  • Onboard voltage regulators for single power rail operation
  • FPGA configuration via JTAG and USB
  • Maximum IOs for user-defined purposes
    • FPGA – 130 IOs
    • FT2232H – 8 IOs


  • Product Prototype Development
  • Accelerated computing integration
  • Development and testing of custom embedded processors
  • Signal Processing
  • Communication devices development
  • Educational tool for Schools and Universities

How to use Narvi Spartan 7 FPGA Module

The following sections describe in detail how to use this module.

Hardware Accessories Required

For easy and fast installation, you may need the following items along with the Narvi module.

  • USB A to Micro B cable
  • DC Power supply
  • A Xilinx Platform Cable USB II compatible JTAG programmer (optional)

Connection Diagram

The following connection diagram should be used for reference only. The schematics are available at the end of this document for detailed information.

USB Interface

The onboard high speed USB controller helps a PC/Linux/Mac computer to communicate with this module. Use a USB A to Micro B cable to connect with a PC.

By default, the module is powered by USB so make sure not to overcrowd unpowered USB hubs (the picture on the right shows Micro B connector)


DC Power Supply

The board is configured to use power from DC power supply by connecting it to the External DC Jack. Please refer to the marking on the board for more details. The external power supply should be in the range of +7 to +12V, with sufficient current rating.

JTAG Connector

JTAG connector allows the FPGA’s JTAG registers to be accessed using a JTAG cable, compatible with Xilinx Platform Cable USB. Use this header, to attach JTAG cable for programming and debugging.

Reset Button and LED

Narvi S7 features a Push-button S2 normally meant to be used as “Reset” signal for designs running on FPGA. Push-button S2 is connected to FPGA pin T14. Push-button S2 is active-high. This push button can also be used for any other input and is not just limited to be used as a Reset signal.

Narvi S7 also features a general purpose LED D6 which can be used in the RTL design as per requirement. LED D6 is connected to FPGA pin G13. LED D6 is active-low.

PROG_B Button

Narvi features a Push-button S1 normally meant to be used as “PROG_B” signal for configuration reset. Push-button S1 is connected to FPGA pin R8. For enabling manual configuration reset, push-button S1 is connected to GND. The user can reconfigure the FPGA manually, by pressing this push-button S1.

“PROG_B” is active-low input pin (pulled up with 4.7K external resistor) to the FPGA and it controls the configuration logic. An assertion followed by de-assertion cycle on PROG_B pin resets the FPGA and initializes the new configuration.

JTAG/SPI Configuration on FT2232H Channel B

Channel B of FT2232H can be connected to the SPI bus that connects the SPI Flash chip to the FPGA or to the JTAG pins of the FPGA. When FT2232H channel B is connected to FPGA JTAG, the JTAG signals can be accessed directly through FT2232H. This is the default configuration set when Narvi S7  is shipped.

Please see the tables below for information about selecting SPI or JTAG for FT2232H channel B.

Solder Jumpers P2

Jumper Configuration for SPIJumper Configuration for JTAG
1 - 2 (S1)1 - 3 (J1)
5 - 6 (S2)4 - 6 (J2)

Solder Jumpers P3

Jumper Configuration for SPIJumper Configuration for JTAG
1 - 2 (S3)1 - 3 (J3)
5 - 6 (S4)4 - 6 (J4)

By default, Narvi S7 ships with the solder jumpers in JTAG configuration. During normal usage, users should not change these jumpers from their factory default configuration.


This device is equipped with a maximum 130 user IO pins that can be used for various custom applications. All user IOs are length matched and can be used as differential pairs.

Header P4

Pin No. On The HeaderGPIO Pin Name Spartan-7 (CSGA324) Pin No.Pin No. On The HeaderGPIO Pin Name Spartan-7 (CSGA324) Pin No.Pin No. On The HeaderGPIO Pin Name Spartan-7 (CSGA324) Pin No.Pin No. On The HeaderGPIO Pin Name Spartan-7 (CSGA324) Pin No.

Header P5

Pin No. On The HeaderGPIO Pin NameSpartan-7 (CSGA324) Pin No.Pin No. On The HeaderGPIO Pin NameSpartan-7 (CSGA324) Pin No.Pin No. On The HeaderGPIO Pin NameSpartan-7 (CSGA324) Pin No.Pin No. On The HeaderGPIO Pin NameSpartan-7 (CSGA324) Pin No.

* BCBUS0 – BCBUS7 are pins of FTDI FT2232H Dual-Channel USB device.

FT2232H - Spartan-7 (CSGA324) FPGA Connection Details

FTDI Pin No.Pin Function (245 FIFO)Spartan 7 (CSGA324) Pin No.

Driver Installation


This product requires a driver to be installed for proper functioning when used with Windows. The Numato Lab Narvi S7 driver can be downloaded from here. When driver installation is complete, the module should appear in Tenagra FPGA System Management Software as Narvi Spartan 7 FPGA Module.


The Linux ships with the drivers required for Narvi S7. It should be enough to run the following two commands in the terminal:

>> sudo modprobe ftdi_sio
>> echo 2a19 100D > /sys/bus/usb-serial/drivers/ftdi_sio/new_id

Generating Bitstream Using Vivado

The bitstream can be generated for Narvi in Vivado by following the steps below:

Step 1: It is recommended to generate .bin bitstream file along with .bit bitstream file. Click “Bitstream Settings”.


Step 2: Select “-bin_file*” option in the dialog window and Click OK.

Step 3: Finally click “Generate Bitstream”.


Programming Narvi Using JTAG

Narvi Spartan 7 FPGA Module features an onboard JTAG connector which facilitates easy reprogramming of SRAM and onboard SPI flash through JTAG programmer like “Xilinx Platform cable USB”. Following steps illustrate how to program FPGA on Narvi using JTAG.

Step 1: By using JTAG cable, connect Xilinx platform cable USB to Narvi and power it up.

Step 2: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 3: If the device is detected successfully, then select “Program Device” after right clicking on the target device “xc7s50_0 (1)” as shown below.

Step 4: In the dialog window which opens up, Vivado automatically chooses correct bitstream file if the design was synthesized, implemented and bitstream generated successfully. If needed, browse to the bitstream which needs to be programmed to FPGA. Finally, click “Program”.

As soon as “Program” is clicked, a green colored DONE LED (D1) on Narvi should light up, indicating that programming process is going on. This LED will turn off when the configuration is complete.

Programming QSPI Flash using Vivado

A .bin or .mcs file is required for programming Narvi’s onboard QSPI flash.

Step 1: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 2: If the device is detected successfully, then select “Add Configuration Memory Device” after right clicking on the target device “xc7s50_0” as shown below.

Step 3: Select the memory device “mt25ql128-spi-x1_x2_x4 (which is equivalent to n25q128-3.3v-spi-x1_x2_x4)”, then click OK.

Step 4: After completion of Step 3 the following dialog box will open. Click OK.

Step 5: Browse to the working .bin file or the .mcs file (whichever applicable) and click OK to program as shown below. If programming is successful, a confirmation message will be displayed.

Programming Narvi Using Tenagra

For steps on how to program Narvi using Tenagra, refer the Getting started with Tenagra FPGA System Management Software article.

Technical Specifications

Parameter *ValueUnit
Basic Specifications
Number of GPIOs130
On-board oscillator frequency (ASEM1-100.000MHZ-LC-T)100MHz
DDR3 SDRAM (MT41J128M16HA - 125 or Equivalent)2Gb
Quad SPI Flash Memory (N25Q128A13ESE40E)128Mb
Power supply voltage (USB or External)5 - 12V
FPGA Specifications
Internal supply voltage relative to GND -0.5 to 1.1 V
Auxiliary supply voltage relative to GND -0.5 to 2.0V
Output drivers supply voltage relative to GND -0.5 to 3.6V

Mechanical Dimensions

Vivado XDC Constraints


Narvi GPIO Trace Length Details

Narvi GPIO Easy Reference

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