Xilinx Artix Ultrascale+ Boards

Introducing the Mimas AU-Plus Development Module – Your Gateway to FPGA Innovation!

Mimas AU-Plus Development Module is an easy to use FPGA Development Module featuring Artix Ultrascale+ FPGA (XCAU7P-1SBVC484 package).

• Device: Xilinx Artix Ultrascale+ FPGA (XCAU7P-1SBVC484). 
• SDRAM – DDR4 (MT40A512M16LY-075:E).
• Flash Memory: 1 Gb SPI flash memory (MT25QU01GBBB8E12-0AAT).
• 1 x Gigabit Ethernet PHY. 
• FTDI FT2232H based host interface. 
• M.2 Connector Interface, M-Key. 
• 100MHz CMOS oscillator (Fabric clock). 
• 100MHz DDR4 Reference Clock. 
• EEPROM. 
• RTC (BQ32000DR). 
• FPGA configuration via JTAG and USB. 
• 40 Differential IOs and two 6×2 Headers for user-defined purposes. 
• 8 LEDs, 4 Push Buttons, 8 DIP switches and 7 Segment display for user-defined purposes. 

• Digital Signal Processing (DSP) Applications
• Networked Systems and IoT Solutions
• Data Storage and Retrieval
• High-Speed Storage Solutions
• Embedded Systems Development
• Prototyping and Rapid Development
• Educational and Research Initiatives
• Robotics and Automation

The following sections describe in detail how to use this module.

• 12V DC Power Supply.
• Xilinx Platform Cable USB II JTAG debugger.
• USB Type C cable.

PROG_B Button

Mimas AU-Plus features a Push-button S1 normally meant to be used as a “PROG_B” signal for configuration reset. Push-button S1 is connected to FPGA pin C7. For enabling manual configuration reset, push-button S1 is connected to GND. The user can reconfigure the FPGA manually, by pressing this push-button S1.

“PROG_B” is an active-low input pin (pulled up with 4.7K external resistor) to the FPGA and it controls the configuration logic. When the PROG_B pin is de-asserted, resets the FPGA and initializes the new configuration.

Reset Button

Mimas AU-Plus features a Push-button S2 normally meant to be used as a “Reset” signal for designs running on FPGA. Push-button S2 is connected to FPGA pin U15. Push-button S2 is active-high. This pushbutton can also be used for any other input and is not just limited to be used as a Reset signal.

This version of the board features four 7-segment LED displays. Each module can be separately turned on and off with the four switching transistors.

Note: All signals (a, b, c, d, e, f, g, dot, enable 1, enable 2, enable 3, enable 4) used for controlling 7-Segment display are active-low signals. So, for example, for displaying “8” in display-2, users need to drive Enable 2 to 0 as well as drive signals a, b, c, d, e, f to 0. All other signals need to be driven to 1.

The Mimas AU-Plus Development Module has 1 Gb of Quad bit SPI flash memory. It is a serial NOR flash which operates at the voltage of 1.8 V. It serves as the default primary boot device.

Mimas AU-Plus Development Module uses DDR4(MT40A512M16LY-075:E) which is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. DDR4 is connected to the bank 66 of Artix Ultrascale+ FPGA.

Fabric clock

DDR4 Reference Clock

Channel A of FT2232H can be connected to the SPI bus that connects the SPI Flash chip to the FPGA or to the JTAG pins of the FPGA. When FT2232H channel A is connected to FPGA JTAG, the JTAG signals can be accessed directly through FT2232H.

Please see the tables below for information about selecting SPI or JTAG for FT2232H channel A

Solder Jumpers P11

Solder Jumpers P12

M.2 edge-connector on Aller provides the power to the board. Each lane is capable of 5GT/s resulting in maximum theoretical data transfer rate of 2 GB/s for all 4 lanes combined.

P2

P3

PMOD_0

PMOD_1

Mimas AU-Plus Development Module features an onboard JTAG connector which facilitates easy reprogramming of SRAM and onboard SPI flash through JTAG programmer like “Xilinx Platform cable USB”. Following steps illustrate how to program FPGA on Mimas using JTAG.

Step 1: By using JTAG cable, connect Xilinx platform cable USB to Mimas AU+ and power it up.

Step 2: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 3: If the device is detected successfully, then select “Program Device” after right clicking on the target device “XCAU7P_0” as shown below.

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Step 4: In the dialog window which opens up, Vivado automatically chooses correct bitstream file if the design was synthesized, implemented and bitstream generated successfully. If needed, browse to the bitstream which needs to be programmed to FPGA. Finally, click “Program”.

A .bin or .mcs file is required for programming Mimas AU-Plus onboard QSPI flash.

Step 1: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 2: If the device is detected successfully, then select “Add Configuration Memory Device” after right clicking on the target device “XCAU7P_0” as shown below.

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Step 3: Select the memory device “mt25ql128-spi-x1_x2_x4 (which is equivalent to n25q128-3.3v-spi-x1_x2_x4)”, then click OK.

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Step 4: After completion of Step 3 the following dialog box will open. Click OK.

Step 5: Browse to the working .bin file or the .mcs file (whichever applicable) and click OK to program as shown below. If programming is successful, a confirmation message will be displayed.

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