AMD Artix Ultrascale+ Boards

Mimas AU-Plus Development Module

0 views January 24, 2024 megha-m 0

Introduction 

Introducing the Mimas AU-Plus Development Module – Your Gateway to FPGA Innovation!

Mimas AU-Plus Development Module is an easy-to-use FPGA Development Module featuring Artix Ultrascale+ FPGA (XCAU7P-1SBVC484 package). The FT2232H brings versatile USB-to-serial connectivity, while DDR4 support enhances data processing efficiency. The inclusion of Gigabit Ethernet facilitates seamless networking, opening doors to IoT and cloud computing applications. Storage is swift and reliable with QSPI flash. The addition of SYZYGY and PMOD connectors enhances flexibility, allowing easy interfacing with sensors and peripherals for customized projects.

In essence, the AU-Plus Development Module is a compact, feature-rich solution for FPGA development, empowering both seasoned developers and enthusiasts to explore limitless possibilities in embedded systems and digital design.

Board Features

  • Device: AMD Artix Ultrascale+ FPGA (XCAU7P-1SBVC484).
  • SDRAM – DDR4.
  • Flash Memory: 1 Gb SPI flash memory.
  • 1 x Gigabit Ethernet PHY.
  • FTDI FT2232H based host interface.
  • 100MHz CMOS oscillator (Fabric clock).
  • 100MHz DDR4 Reference Clock.
  • FPGA configuration via JTAG and USB.
  • 2x TXR-2 and 1x standard SYZYGY connector.
  • 2x PMOD.
  • 8 LEDs, 4 Push Buttons, 8 DIP switches and 7 Segment display for user-defined purposes.

 

Application 

  • Digital Signal Processing (DSP) Applications
  • Networked Systems and IoT Solutions
  • Data Storage and Retrieval
  • High-Speed Storage Solutions
  • Embedded Systems Development
  • Prototyping and Rapid Development
  • Educational and Research Initiatives
  • Robotics and Automation

How to use Mimas AU-Plus Development Module

The following sections describe in detail how to use this module.

Hardware Accessories Required 

 

  • 5V DC Power Supply.
  • Xilinx Platform Cable USB II JTAG debugger.
  • USB Type C cable.

Connection Diagram 

Please note that the diagram provided is intended solely as a reference.

USB Interface 

The onboard high speed USB controller helps a PC/Linux/Mac computer to communicate with this module. Use a USB C cable to connect with a PC.
By default, the module is powered by USB so make sure not to overcrowd unpowered USB hubs (the picture on the right shows C connector).

DC Power Supply

The board is configured to use power from DC power supply by connecting it to the External DC Jack. Please refer to the marking on the board for more details. The external power supply should be 5V, with sufficient current rating.

JTAG Connector

JTAG connector allows the FPGA’s JTAG registers to be accessed using a JTAG cable, compatible with Xilinx Platform Cable USB. Use this header, to attach JTAG cable for programming and debugging.

PROG_B and Reset Buttons

PROG_B Button

Mimas AU-Plus features a Push-button S1 normally meant to be used as a “PROG_B” signal for configuration reset. Push-button S1 is connected to FPGA pin C7. For enabling manual configuration reset, push-button S1 is connected to GND. The user can reconfigure the FPGA manually, by pressing this push-button S1.

“PROG_B” is an active-low input pin (pulled up with 4.7K external resistor) to the FPGA and it controls the configuration logic. When the PROG_B pin is de-asserted, resets the FPGA and initializes the new configuration.

Reset Button

Mimas AU-Plus features a Push-button S2 normally meant to be used as a “Reset” signal for designs running on FPGA. Push-button S2 is connected to FPGA pin U14. Push-button S2 is active-high. This pushbutton can also be used for any other input and is not just limited to be used as a Reset signal.

 

LED, Push Button and Dip Switch

Mimas AU-Plus Development Module has four push-button switches, an eight-position DIP switch and eight LEDs for human interaction. All switches are directly connected to Artix Ultrascale Plus FPGA and can be used in your design with minimal effort.

7-Segment LED Display

The board features four 7-segment LED displays. Each module can be separately turned on and off with the four switching transistors.

Note: All signals (a, b, c, d, e, f, g, dot, enable 1, enable 2, enable 3, enable 4) used for controlling 7-Segment display are active-low signals.

For example, to display “8” on display-2, users should set Enable 2 to 0 and drive signals a, b, c, d, e, and f to 0, while setting all other signals to 1.

Gigabit Ethernet

The KSZ9031RNX is a completely integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physical layer transceiver for transmission and reception of data. It provides the Reduced Gigabit Media Independent Interface (RGMII) for direct connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at 10/100/1000 Mbps.

SPI FLASH

The Mimas AU-Plus Development Module has 128 Mbit of Quad SPI flash memory. It is a serial NOR flash which operates at the voltage of 1.8 V. It serves as the default primary boot device.

DDR4

Mimas AU-Plus Development Module uses DDR4(AS4C512M16D4B-62BCN) which is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. DDR4 is connected to the bank 66 of Artix Ultrascale Plus FPGA.

Reference clock

Fabric clock

Clock pinsFPGA pins
REF_CLK_PK18
REF_CLK_NJ18

DDR4 Reference Clock

Clock pinsFPGA pins
DDR4_REFCLK_PB14
DDR4_REFCLK_NB15

FT2232H - Artix Ultrascale Plus (1SBVC484) FPGA Connection Details

FTDI Pin No. Pin Function Signal nameFPGA pins
38FTDI-D0IO_L6P_HDGC_84Y6
39FTDI-D1IO_L5N_HDGC_84AB7
40FTDI-D2IO_L5P_HDGC_84AA7
41FTDI-D3IO_L4N_AD12N_84AB8
43FTDI-D4IO_L4P_AD12N_84AA8
44FTDI-D5IO_L2N_AD14N_84AB9
45FTDI-D6IO_L3P_AD13P_84Y10
46FTDI-D7IO_L1N_AD15N_84AB10
48FTDI-RXF#IO_L8P_HDGC_84V9
52FTDI-TXE#IO_L7N_HDGC_84Y8
53FTDI-RD#IO_L3N_AD13N_84Y9
54FTDI-WR#IO_L1P_AD15P_84AA11
55FTDI-SIWUAIO_L2P_AD14P_84AA10

SYZYGY Connectors

SYZYGY PORT A

Pin No. On The HeaderPin NameSignal nameFPGA PinPin No. On The HeaderPin NameSignal nameFPGA Pin
1SYZYGY_PORT_SCLIO_L9P_AD11P_84U102VIN
3SYZYGY_PORT_SDAIO_L9N_AD11N_84V104GND
5SZG_PORTA_RX0_PMGTHRXP0_124AA216SZG_PORTA_TX0_PMGTHTXP0_124AB19
7SZG_PORTA_RX0_NMGTHRXN0_124AA228SZG_PORTA_TX0_NMGTHTXN0_124AB20
9SZG_PORTA_RX1_PMGTHRXP1_124W2110SZG_PORTA_TX1_PMGTHTXP1_124Y19
11SZG_PORTA_RX1_NMGTHRXN1_124W2212SZG_PORTA_TX1_NMGTHTXN1_124Y20
13SZG_PORTA_REFCLK_PMGTREFCLK0P_124AA1714SZG_PORTA_S0IO_L10P_AD2P_86B5
15SZG_PORTA_REFCLK_NMGTREFCLK0N_124AA1816SZG_PORTA_S1IO_L10N_AD2N_86A5
17SZG_PORTA_S2IO_L2P_AD10P_86F318SZG_PORTA_S3IO_L9P_AD3P_86C5
19SZG_PORTA_S4IO_L2N_AD10N_86E320SZG_PORTA_S5IO_L9N_AD3N_86B4
21SZG_PORTA_S6IO_L4P_AD8P_86G222SZG_PORTA_S7IO_L11P_AD1P_86B3
23SZG_PORTA_S8IO_L4N_AD8N_86F224SZG_PORTA_S9IO_L11N_AD1N_86A3
25SZG_PORTA_S10IO_L3P_AD9P_86E426SZG_PORTA_S11IO_L12P_AD0P_86B2
27SZG_PORTA_S12IO_L3N_AD9N_86D328SZG_PORTA_S13IO_L12N_AD0N_86A2
29SZG_PORTA_S14IO_L5P_HDGC_D7P_86F130SZG_PORTA_S15IO_L8P_HDGC_AD4P_86D4
31SZG_PORTA_S16IO_L5N_HDGC_AD7N_86E132SZG_PORTA_S17IO_L8N_HDGC_AD4N_86C4
33SZG_PORTA_P2C_CLK_PIO_L6P_HDGC_AD6P_86D134SZG_PORTA_C2P_CLK_PIO_L7P_HDGC_AD5P_86D2
35SZG_PORTA_P2C_CLK_NIO_L6N_HDGC_AD6N_86C136SZG_PORTA_C2P_CLK_NIO_L7N_HDGC_AD5N_86C2
37RSVD38RSVDE5
39VIOA40VDD3V3

SYZYGY PORT B

Pin No. On The HeaderPin NameSignal nameFPGA PinsPin No. On The HeaderPin NameSignal nameFPGA Pins
1SYZYGY_PORT_SCLIO_L9P_AD11P_84U102VIN
3SYZYGY_PORT_SDAIO_L9N_AD11N_84 V104GND
5SZG_PORTB_RX2_PMGTHRXP2_124U216SZG_PORTB_TX2_PMGTHTXP2_124V19
7SZG_PORTB_RX2_NMGTHRXN2_124U228SZG_PORTB_TX2_NMGTHTXN2_124V20
9SZG_PORTB_RX3_PMGTHRXP3_124R2110SZG_PORTB_TX3_PMGTHTXP3_124T19
11SZG_PORTB_RX3_NMGTHRXN3_124R2212SZG_PORTB_TX3_NMGTHTXN3_124T20
13SZG_PORTB_REFCLK_PMGTREFCLK1P_124U1714SZG_PORTB_S0IO_L8P_HDGC_104Y5
15SZG_PORTB_REFCLK_NMGTREFCLK1N_124U1816SZG_PORTB_S1IO_L8N_HDGC_104AA5
17SZG_PORTB_S2IO_L2P_AD14P_104AB318SZG_PORTB_S3IO_L9P_AD11P_104U5
19SZG_PORTB_S4IO_L2N_AD14N_104AB220SZG_PORTB_S5IO_L9N_AD3N_86B4
21SZG_PORTB_S6IO_L3P_AD13P_104Y322SZG_PORTB_S7IO_L10P_AD10P_104U4
23SZG_PORTB_S8IO_L3N_AD13N_104AA324SZG_PORTB_S9IO_L10N_AD10N_104V4
25SZG_PORTB_S10IO_L4P_AD12P_104AA226SZG_PORTB_S11IO_L11P_AD9P_104U3
27SZG_PORTB_S12IO_L4N_AD12N_104AA128SZG_PORTB_S13IO_L11N_AD9N_104V2
29SZG_PORTB_S14IO_L5P_HDGC_104W130SZG_PORTB_S15IO_L12P_AD8P_104U2
31SZG_PORTB_S16IO_L5N_HDGC_104Y132SZG_PORTB_S17IO_L12N_AD8N_104V1
33SZG_PORTB_P2C_CLK_PIO_L6P_HDGC_104W334SZG_PORTB_C2P_CLK_PIO_L7P_HDGC_104W4
35SZG_PORTB_P2C_CLK_NIO_L6N_HDGC_104W236SZG_PORTB_C2P_CLK_NIO_L7N_HDGC_104Y4
37RSVD38RSVD
39VIO40VDD3V3

SYZYGY PORT C

Pin No. On The HeaderPin NameSignal nameFPGA PinsPin No. On The HeaderPin NameSignal nameFPGA Pins
1SYZYGY_PORT_SCLIO_L9P_AD11P_84U102VIN
3SYZYGY_PORT_SDAIO_L9N_AD11N_84V104GND
5SZG_PORTC_D0_PIO_L1P_T0L_N0_DBC_RS0_65R176SZG_PORTC_D1_PIO_L6P_T0U_N10_AD6P_A20_65M15
7SZG_PORTC_D0_NIO_L1N_T0L_N1_DBC_RS1_65P188SZG_PORTC_D1_NIO_L6N_T0U_N11_AD6N_A21_65L16
9SZG_PORTC_D2_PIO_L2P_T0L_N2_FOE_B_65R1510SZG_PORTC_D3_PIO_L19P_T3L_N0_DBC_AD9P_D10_65F21
11SZG_PORTC_D2_NIO_L2N_T0L_N3_FWEFCS2_B_65R1612SZG_PORTC_D3_NIO_L19N_T3L_N1_DBC_AD9N_D11_65F22
13SZG_PORTC_D4_PIO_L3P_T0L_N4_AD15P_A26_65P1614SZG_PORTC_D5_PIO_L5P_T0U_N8_AD14P_A22_65L17
15SZG_PORTC_D4_NIO_L3N_T0L_N5_AD15N_A27_65P1716SZG_PORTC_D5_NIO_L5N_T0U_N9_AD14N_A23_65L18
17SZG_PORTC_D6_PIO_L4P_T0U_N6_DBC_AD7P_A24_65N1518SZG_PORTC_D7_PIO_L20P_T3L_N2_AD1P_D08_65H22
19SZG_PORTC_D6_NIO_L4N_T0U_N7_DBC_AD7N_A25_65N1620SZG_PORTC_D7_NIO_L20N_T3L_N3_AD1N_D09_65G22
21SZG_PORTC_S16IO_T1U_N12_SMBALERT_65N2022SZG_PORTC_S17IO_L23P_T3U_N8_I2CSCLK_65H19
23SZG_PORTC_S18IO_L17P_T2U_N8_AD10P_D14_65G1824SZG_PORTC_S19IO_L23N_T3U_N9_ERSTN1_I2C_SDA_65G20
25SZG_PORTC_S20IO_L24P_T3U_N10_EMCCLK_65G1926SZG_PORTC_S21IO_L15P_T2L_N4_AD11P_A02_D18_65K15
27SZG_PORTC_S22IO_L24N_T3U_N11_DOUT_CSO_B_65 F2028SZG_PORTC_S23IO_L15N_T2L_N5_AD11N_A03_D19_65J16
29SZG_PORTC_S24IO_L18N_T2U_N11_AD2N_D13_65F1630SZG_PORTC_S25IO_L21P_T3L_N4_AD8P_D06_65J21
31SZG_PORTC_S26IO_L8P_T1L_N2_AD5P_A16_65M2232SZG_PORTC_S27IO_L21N_T3L_N5_AD8N_D07_65J22
33SZG_PORTC_P2C_CLK_PIO_L22P_T3U_N6_DBC_AD0P_D04_65J1934SZG_PORTC_C2P_CLK_PIO_L7P_T1L_N0_QBC_AD13P_A18_65L21
35SZG_PORTC_P2C_CLK_NIO_L22N_T3U_N7_DBC_AD0N_D05_65H2036SZG_PORTC_C2P_CLK_NIO_L7N_T1L_N1_QBC_AD13N_A19_65K21
37RSVD38RSVD
39VIO40VDD3V3

 

PMOD HEADERS

By default the PMOD header are high.

PMOD_0

Pin No. On The HeaderPMOD Pin NameSignal nameFPGA PINPin No. On The HeaderPMOD Pin Name FPGA PIN
6VCC12VCC
5GND11GND
4CONN0_D4IO_L3P_AD13P_85Y1110CONN0_D8IO_L3N_AD13N_85AA12
3CONN0_D3IO_L2P_AD14P_85AB129CONN0_D7IO_L2N_AD14N_85AB13
2CONN0_D2IO_L5P_HDGC_85Y158CONN0_D6IO_L5N_HDGC_85AA15
1CONN0_D1IO_L1P_AD15P_85AB147CONN0_D5IO_L1N_AD15N_85AB15

PMOD_1

Pin No. On The HeaderPMOD Pin NameSignal nameFPGA PINPin No. On The HeaderPMOD Pin NameSignal nameFPGA PIN
6VCC12VCC
5GND11GND
4CONN1_D4IO_L8P_HDGC_85V1210CONN1_D8IO_L8N_HDGC_85W12
3CONN1_D3IO_L7P_HDGC_85V149CONN1_D7IO_L7N_HDGC_85W14
2CONN1_D2IO_L6P_HDGC_85W138CONN1_D6IO_L6N_HDGC_85Y14
1CONN1_D1IO_L4P_AD12P_85Y137CONN1_D5IO_L4N_AD12N_85AA13

Generating Bitstream for Mimas AU-Plus

The bitstream can be generated for Mimas AU-Plus in Vivado by following the steps below:

Step 1: It is recommended to generate a .bin bitstream file along with .bit bitstream file. Click “Bitstream Settings”.

Step 2: In the window that pops up, select the “-bin_file” option and click OK.


Step 3: Finally click “Generate Bitstream”.

Programming Mimas AU-Plus Using USB-JTAG

Ensure that the D2XX drivers are installed prior to programming.  The channel A of FTDI FT2232H chip on Mimas AU-Plus board is connected to the JTAG interface of the FPGA. Through this connection, USB interface can be used as a JTAG programmer, eliminating the need for a dedicated JTAG cable or connector. Following steps illustrate how to program FPGA on Mimas AU-Plus using USB.

1. Ensure that switch SW2 (PGM SEL) is set to USB mode and Connect the USB Type-C cable to the FPGA board.

2. Click on “Auto connect” under hardware manager and it will automatically establish the connection.

Programming Mimas AU-Plus Using JTAG

Mimas AU-Plus Development Module features an onboard JTAG connector which facilitates easy reprogramming of SRAM and onboard SPI flash through JTAG programmer like “Xilinx Platform cable USB”. Following steps illustrate how to program FPGA on Mimas AU-Plus using JTAG.

Step 1: Ensure that switch SW2 is set to JTAG mode.

Step 2: By using JTAG cable, connect Xilinx platform cable USB to Mimas AU-Plus and power it up.

Step 3: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 4: If the device is detected successfully, then select “Program Device” after right clicking on the target device “XCAU7P_0” as shown below.

Step 5: In the dialog window which opens up, Vivado automatically chooses correct bitstream file if the design was synthesized, implemented and bitstream generated successfully. If needed, browse to the bitstream which needs to be programmed to FPGA. Finally, click “Program”.

As soon as “Program” is clicked, a orange colored DONE LED (D1) on Mimas AU-Plus should light up, indicating that programming process is going on. This LED will turn off when the configuration is complete.

Programming QSPI Flash using Vivado

A .bin or .mcs file is required for programming Mimas AU-Plus onboard QSPI flash.

Step 1: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 2: If the device is detected successfully, then select “Add Configuration Memory Device” after right clicking on the target device “XCAU7P_0” as shown below.

Step 3: Select the memory device “mt25ql128-spi-x1_x2_x4 (which is equivalent to n25q128-3.3v-spi-x1_x2_x4)”, then click OK.

Step 4: After completion of Step 3 the following dialog box will open. Click OK.

Step 5: Browse to the working .bin file or the .mcs file (whichever applicable) and click OK to program as shown below. If programming is successful, a confirmation message will be displayed.

Technical Specifications

Parameter ValueUnit
Basic Specifications
Number of PMODs2
On-board oscillator frequency (ASDMPLV-100.000MZ-LR-T3)100MHz
Quad SPI Flash Memory(MT25QU128ABA1ESE-0SIT TR)
128Mb
DDR4(AS4C512M16DB-62BCN)
8Gb
Syzygy connectors3
Power supply voltage (USB or External)5V
Operating Temperature0-70°C
Number of LEDs8
Number of Push Buttons4
Number of Dip Switches8
FPGA Specifications
Internal supply voltage relative to GND-0.5 to 1.0V
Auxiliary supply voltage relative to GND-0.5 to 2.0V
Output drivers supply voltage for HD I/O banks–0.500 to 3.400V
Output drivers supply voltage for HP I/O banks and configuration bank 0 –0.500 to 2.000V

Mechanical Dimensions

Vivado XDC Constraints

Mimas AU-Plus IO length details

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