Xilinx Kintex 7 FPGA Boards

Callisto Kintex 7 USB 3.1 FPGA Module

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Introduction

Callisto K7 is an easy to use FPGA Module featuring the Xilinx Kintex 7 FPGA with 4Gb DDR3 SDRAM. This board contains the Xilinx XC7K410T– FBG676 FPGA. The high-speed USB 3.1 interface (USB-C connector) provides fast and easy configuration download to the onboard SPI flash. There is no need for a programmer or special downloader cable to download bitstream to the board. The FPGA Module also provides easy access to JTAG signals on a standard Xilinx Platform Cable compatible header. Callisto K7 provides the user the flexibility of adding their own peripherals through IO Expansion Headers.

Board Features

  • FPGA: Kintex XC7K410T in FBG676 package
  • DDR3: 4Gb DDR3 (MT41J256M16HA-125:K or equivalent)
  • Flash memory: 1 Gb Quad SPI flash memory (MT25QL01GBBB)
  • 1 x 100MHz CMOS oscillator
  • USB 3.1 Gen1 @5Gbps (USB Type-C connector)
  • Onboard voltage regulators for single power rail operation
  • 12V DC power supply
  • A Push Button for the reset pin
  • JTAG header for programming and debugging.
  • Maximum IOs for user-defined purposes
    • FPGA – 274 IOs

Applications

  • Product Prototype Development
  • Communication Devices Development
  • Accelerated Computing Integration
  • Development and Testing of Custom embedded processors
  • Signal Processing
  • Educational tool for Schools and Universities

How to use Callisto Kintex 7 FPGA Development Board

The following sections describe in detail how to use this module.

Components/Tools Required

Along with the module, you may need the accessories listed below for easy and fast installation:

  1. 12 V DC Power Supply.
  2. USB A to USB-C cable (Optional).
  3. A Xilinx Platform Cable USB II compatible JTAG programmer

Connection Diagram

This diagram should be used as a reference only. For detailed information, see Callisto K7’s schematics and mechanical dimensions at the end of this page. Details of individual connectors are as shown below.

USB Interface

This super speed USB 3.1 interface (USB-C connector) is used to help the host PC to communicate with the module at a very high speed (5Gbps). A USB-A to USB-C cable is used to connect the module to the host PC. It is primarily used to output debug information or as a console for the design running on the board. (the picture on the right shows USB-C connector).

DC Power Supply

By default, the board is configured to use +5V supply from USB. So an external power is not required unless USB port is unable to supply enough current. USB 3.1 ports are only capable of providing enough current for the module for small designs which require less power. The current requirement for this board largely depends on your application. Please consult FPGA data sheet for more details on power requirements. If for any reason, an external power supply needs to be used for the board, connect the DC power supply. Please refer to the marking on the board for more details. The external power supply should be in the range of +5 to +12V, with sufficient current rating.

Heat Sink

A Heat Sink comes factory-installed with Callisto K7 to provide for heat dissipation for the Kintex-7 FPGA on board. A header is provided to optionally connect a fan (not factory installed) for forced-cooling. The fan’s speed is controlled by the FAN_PWM signal connected to FPGA IO location N16, and the signal is pulled up by default, which means unless actively driven to 0 or controlled via PWM, the fan will run at maximum speed.

Reset Button

Callisto K7 features a Push-button S1 normally meant to be used as “Reset” signal for designs running on FPGA. Push-button S2 is connected to FPGA pin K21. Push-button S1 is active-high. This push-button can also be used for any other input and is not just limited to be used as a Reset signal.

JTAG Connector

JTAG connector allows the FPGA’s JTAG registers to be accessed using a JTAG cable, compatible with Xilinx Platform Cable USB. Use this header, to attach JTAG cable for programming and debugging.

FT601 - Kintex 7 (FBG676) FPGA Connection Details

FTDI Pin No.Pin Function (245 FIFO)Kintex-7 (FBG676) Pin No.
40FT_D0N17
41FT_D1N18
42FT_D2M19
43FT_D3M20
44FT_D4N19
45FT_D5K25
46FT_D6K26
47FT_D7L24
50FT_D8L25
51FT_D9M24
52FT_D10M25
53FT_D11M26
54FT_D12N22
55FT_D13N24
56FT_D14N26
57FT_D15P16
60FT_D16R16
61FT_D17U16
62FT_D18R17
63FT_D19T17
64FT_D20U17
65FT_D21R18
66FT_D22P26
67FT_D23P25
69FT_D24P24
70FT_D25R26
71FT_D26R25
72FT_D27R23
73FT_D28T25
74FT_D29T24
75FT_D30R22
76FT_D31T22
4FT_BE0P18
5FT_BE1P19
6FT_BE2T18
7FT_BE3T19
8FT_TXEU19
9FT_RXER20
11FT_WRR21
12FT_RDP21
13FT_OET20
15FT_RSTU20
16FT_WKT23
58FT_CLKN21

GPIOs

This device is equipped with a maximum of 274 user IO pins that can be used for various custom applications. All user IOs are length matched and can be used as differential pairs.

Header P1

PIN NO. ON HEADERKintex 7 (XC7K410T-1FBG676)PIN NO. ON HEADERKintex 7 (XC7K410T-1FBG676)PIN NO. ON HEADERKintex 7 (XC7K410T-1FBG676)PIN NO. ON HEADERKintex 7 (XC7K410T-1FBG676)PIN NO. ON HEADERKintex 7 (XC7K410T-1FBG676)PIN NO. ON HEADERKintex 7 (XC7K410T-1FBG676)
A1EXT_VCCB1EXT_VCCC1EXT_VCCD1EXT_VCCE1EXT_VCCF1EXT_VCC
A2GNDB2GNDC2GNDD2GNDE2GNDF2GND
A3GNDB3K23C3J23D3GNDE3J24F3J25
A4J21B4H22C4GNDD4L22E4K22F4GND
A5GNDB5F25C5E26D5GNDE5H23F5H24
A6G24B6F24C6GNDD6J26E6H26F6GND
A7GNDB7G22C7F23D7GNDE7G25F7G26
A8D26B8C26C8GNDD8H21E8G21F8GND
A9GNDB9D23C9D24D9GNDE9E25F9D25
A10D21B10C22C10GNDD10E21E10E22F10GND
A11GNDB11C21C11B21D11GNDE11A23F11A24
A12K15B12M16C12GNDD12B20E12A20F12GND
A13GNDB13C16C13B16D13GNDE13C17F13C18
A14B17B14A17C14GNDD14C19E14B19F14GND
A15GNDB15H16C15G16D15GNDE15A18F15A19
A16G15B16F15C16GNDD16J15E16J16F16GND
A17GNDB17D15C17D16D17GNDE17E18F17D18
A18E15B18E16C18GNDD18F17E18E17F18GND
A19GNDB19G17C19F18D19GNDE19F19F19E20
A20H17B20H18C20GNDD20G19E20F20F20GND
A21GNDB21D19C21D20D21GNDE21L19F21L20
A22H19B22G20C22GNDD22J18E22J19F22GND
A23GNDB23K20C23J20D23GNDE23M17F23L18
A24K16B24K17C24GNDD24L17E24K18F24GND
A25GNDB25J8C25J14D25GNDE25B15F25A15
A26B14B26A14C26GNDD26F14E26F13F26GND
A27GNDB27C14C27C13D27GNDE27G12F27F12
A28A13B28A12C28GNDD28E13E28E12F28GND
A29GNDB29D14C29D13D29GNDE29G11F29F10
A30B12B30B11C30GNDD30E11E30D11F30GND
A31GNDB31B10C31A10D31GNDE31G10F31G9
A32A9B32A8C32GNDD32H9E32H8F32GND
A33GNDB33C9C33B9D33GNDE33H14F33G14
A34C12B34C11C34GNDD34J13E34H13F34GND
A35GNDB35D9C35D8D35GNDE35H12F35H11
A36E10B36D10C36GNDD36J11E36J10F36GND
A37GNDB37F9C37F8D37GNDE37NCF37NC
A38NCB38NCC38GNDD38NCE38NCF38GND
A39GNDB39GNDC39GNDD39GNDE39GNDF39GND
A40VADJ_B12B40VADJ_B15C40VADJ_B16D40VADJ_B32E40VBATTF40VCC3V3

Header P2

PIN NO. ON HEADERKintex 7 (XC7K410T-1FBG676)PIN NO. ON HEADERKintex 7 (XC7K410T-1FBG676)PIN NO. ON HEADERKintex 7 (XC7K410T-1FBG676)PIN NO. ON HEADERKintex 7 (XC7K410T-1FBG676)PIN NO. ON HEADERKintex 7 (XC7K410T-1FBG676)PIN NO. ON HEADERKintex 7 (XC7K410T-1FBG676)
A1U24B1U25C1GNDD1U21E1Y20F1GND
A2GNDB2U22C2V22D2GNDE2V23F2V24
A3U26B3V26C3GNDD3V21E3W21F3GND
A4GNDB4W25C4W26D4GNDE4AA25F4AB25
A5W23B5W24C5GNDD5Y25E5Y26F5GND
A6GNDB6AB26C6AC26D6GNDE6AA23F6AB24
A7Y23B7AA24C7GNDD7AC23E7AC24F7GND
A8GNDB8Y22C8AA22D8GNDE8W20F8Y21
A9AD23B9AD24C9GNDD9AB21E9AC21F9GND
A10GNDB10AB22C10AC22D10GNDE10AD21F10AE21
A11AF24B11AF25C11GNDD11AE23E11AF23F11GND
A12GNDB12AD26C12AE26D12GNDE12AD25F12AE25
A13AE22B13AF22C13GNDD13V13E13W13F13GND
A14GNDB14AE17C14AF17D14GNDE14AA17F14AA18
A15AF14B15AF15C15GNDD15AD15E15AE15F15GND
A16GNDB16AE18C16AF18D16GNDE16AB16F16AC16
A17AF19B17AF20C17GNDD17AA14E17AA15F17GND
A18GNDB18AD16C18AE16D18GNDE18AC18F18AD18
A19AC14B19AD14C19GNDD19AB14E19AB15F19GND
A20GNDB20Y15C20Y16D20GNDE20AB17F20AC17
A21AD20B21AE20C21GNDD21AC19E21AD19F21GND
A22GNDB22AA19C22AA20D22GNDE22AB19F22AB20
A23Y17B23Y18C23GNDD23W18E23W19F23GND
A24GNDB24V16C24V17D24GNDE24W15F24W16
A25V18B25V19C25GNDD25V14E25W14F25GND
A26GNDB26AE7C26AF7D26GNDE26U9F26V12
A27AA8B27AA7C27GNDD27AB7E27AC7F27GND
A28GNDB28AC8C28AD8D28GNDE28AA9F28AB9
A29AC9B29AD9C29GNDD29AA10E29AB10F29GND
A30GNDB30AB11C30AC11D30GNDE30AB12F30AC12
A31AA13B31AA12C31GNDD31Y13E31Y12F31GND
A32GNDB32AC13C32AD13D32GNDE32AD10F32AE10
A33AE12B33AF12C33GNDD33AE13E33AF13F33GND
A34GNDB34AE8C34AF8D34GNDE34AF10F34AF9
A35N12B35P11C35GNDD35NCE35NCF35GND
A36NCB36J7C36B24D36A22E36C23F36G7
A37B22B37C8C37A25D37NCE37GNDF37P6
A38VCC3V3B38L8C38N8D38R7E38R6F38GND
A39GNDB39GNDC39GNDD39GNDE39GNDF39GND
A40VCC3V3B40VCC3V3C40VCC3V3D40VCC3V3E40VCC3V3F40VCC3V3

Driver Installation

This product requires a driver to be installed for proper functioning when used with Windows. The D3XX driver can be downloaded from http://www.ftdichip.com/Drivers/D3XX.htm. Callisto K7 also has one FT232 which requires D2XX driver (It can be downloaded from http://www.ftdichip.com/Drivers/D2XX.htm). Windows Users should download and run the latest WHQL Certified executable file that will prompt to install the FTDI CDM drivers. When driver installation is complete, the module should appear in Callisto K7 Flash Config Tool as Callisto Kintex 7 USB 3.1 FPGA Module.

Generating Bitstream Using Vivado

The bitstream can be generated for Callisto K7 in Vivado by following the steps below:

Step 1: It is recommended to generate .bin bitstream file along with .bit bitstream file. Click “Bitstream Settings”.

Step 2: In the window that pops up, select “-bin_file*” option and Click OK.

Step 3: Finally click “Generate Bitstream”.

Powering Up Callisto K7

Callisto K7 is factory configured to be powered directly from USB port so make sure that you are using a USB port that can power the board properly. It is recommended to connect the board directly to the PC instead of using a hub. It is practically very difficult to estimate the power consumption of the board, as it depends heavily on your design and the clock used. XILINX provides tools to estimate the power consumption. In any case, if power from USB is not enough for your application, external supply can be applied to the board. Callisto K7 requires three different voltages, a 3.3V, a 1.8V supplies and a 1.2V supply. Onboard regulators derive these voltages from the USB/Ext power supply.

Programming Callisto K7 Using JTAG

Callisto Kintex-7 USB 3.1 FPGA Module features an onboard JTAG connector which facilitates easy reprogramming of SRAM and onboard SPI flash through JTAG programmer like “Xilinx Platform cable USB”. Following steps illustrate how to program FPGA on Callisto K7 using JTAG.

Step 1: Connect Xilinx Platform cable USB to Callisto K7 using JTAG cable. Power up Callisto K7.

Step 2:  Open Vivado Project. Click on “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 3: If the device is successfully detected, then right click on the “xc7k410t_0(1)”. Select “Program Device” as shown below.

Step 4: In the dialog window which opens up, Vivado automatically chooses the correct bitstream file if the design was synthesized and implemented, and its bitstream was generated successfully. If needed, you can browse to the bitstream which needs to be programmed to the FPGA.

Click on the “Program” button and let the FPGA be programmed. There is a green colored LED (D1) on Callisto K7 which was lights up as an indicator that the FPGA is not programmed. Hence, once the programming process of FPGA is completed, the LED stops glowing.

Programming QSPI Flash using Vivado

A .bin or .mcs file is required for programming Callisto K7’s onboard QSPI flash.

Step 1: Open Vivado Project. Click on “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window.

Step 2: If the device is successfully detected, then right click on the “xc7k410t_0”. Select “Add Configuration Memory Device” as shown below.

 

Step 3: Select the memory device “mt25ql01g-spi-x1_x2_x4”, then click OK.

Step 4: After completion of Step 3 the following dialog box will open. Click OK.

Step 5: Browse to the working .bin file or the .mcs file (whichever applicable) and click OK to program as shown below. If programming is successful, a confirmation message will be displayed.

Technical Specifications

Parameter*ValueUnit
Basic Specifications
Number of GPIOs(max)274
On-board Oscillator Frequency (ASEM1-100.000MHZ-LC-T)100 (x1)MHz
DDR3(MT41J256M16HA-125:K)4 (x1)Gb
Quad SPI Flash Memory (MT25QL01GBBB)1 (x1)Gb
Power Supply voltage (External)5 - 12V
FPGA Specifications
Internal supply voltage relative to GND-0.5 to 1.1V
Auxillary supply voltage relative to GND-0.5 to 2.0V
Output driver supply voltage relative to GND-0.5 to 3.6V

Mechanical Dimensions

Vivado XDC Constraints

Schematics

Callisto K7 GPIO Easy Reference

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