Xilinx Artix 7 FPGA Boards

Tagus is an easy to use FPGA Development Board featuring Xilinx Artix-7 FPGA with x1 PCIe interface, Trusted Platform Module (ATXXXXXX), Dual SFP+ cages, and 2Gb DDR3 SDRAM. This board features Xilinx XC7A200T– FBG484I FPGA. The board features Low Pin Count (LPC) high-speed FMC connector conforming to ANSI/VITA 57.1 Standard for the purpose of adding additional features to the board by using custom or commercial off-the-shelf daughter boards.

Applications:

• Parallel Processing and Accelerators
• Product Prototype Development
• Development and Testing of custom embedded processors
• Signal Processing
• Communication Devices Development
• Data Acquisition
• Educational tool for Schools and Universities

Board features

• FPGA: Artix-7 XC7A200T in -2 FBG484I package
• 1 lane PCIe Gen2.0 (5.0GT/s)
• DDR3: 2Gb DDR3 (MT41J128M16HA-125:K or equivalent)
• 128 Mb QSPI flash memory (N25Q128A13ESE40E) for Configuration and optional data storage
• USB to UART serial converter
• 1 x 100MHz CMOS oscillator
• Maximum 68 IOs for user-defined purposes on ANSI/VITA 57.1 Standard compliant FMC LPC connector
• 1x GTP lanes up to 6.6Gbps on ANSI/VITA 57.1 Standard compliant FMC LPC connector
• 1 RGB LED for custom use
• 1x Trusted Platform Module (ATXXXXXX )
• Dual SFP+ Cages
• MicroSD adapter for bulk data storage
• Onboard voltage regulators for single power rail operation
• Can be powered from PCIe slot or from an external power supply
• JTAG header for programming and debugging
• All differential pairs are length matched on the board

Along with the board, the following accessories are required for easy and fast installation.

1. 12 V DC Power Supply (not needed if the board is inserted into a motherboard)
2. A Xilinx Platform Cable USB II compatible JTAG programmer
3. USB Male A to Micro B cable (optional)

The following diagram should be used as a reference only. For detailed information, see Tagus’s schematics and mechanical dimensions at the end of this page. 

The Tagus requires a +12V power supply to function properly. The Tagus can be supplied power in 3 ways:

1. External +12V power via DC Barrel Jack Connector
2. External +12V power via 3×2 PCIe Power Connector.
3. Via Motherboard when the Tagus is plugged into a PCIe slot that is capable of powering the Tagus

The current requirement for this board largely depends on your application. The Tagus module works on a power supply of 1 A of current for simple applications. However, a power supply 2 A of current is recommended for a smooth running of bigger applications. Please consult the FPGA datasheet for more details on power requirements.

USB Serial Bridge can be used to interface with PC using a serial interface. It is primarily used to output debug information or as a console for the design running on the board. A Micro USB type cable should be used to connect Tagus to host PC. An FT234 is used as the USB-Serial Bridge IC. The USB-Serial interface features hardware flow control using RTS and CTS signals, in case users need to use hardware flow control. An extra signal CBUS0 from FT234X is also connected to FPGA, which can be used as host-controlled GPIO or can be used for other purposes.

JTAG connector allows the FPGA’s JTAG registers to be accessed using a JTAG cable compatible with Xilinx Platform Cable USB. Use this header to attach JTAG cable for programming and debugging.

Tagus features one RGB LED which can be used for custom or debug purposes. The LED is wired in the active-low configuration.

The Tagus board features an onboard Micro SD adapter. You can add the data logging, media storage, and other file storage by installing Micro SD Card and appropriate IP. The connection between FPGA and Micro SD Card is shown below

JTAG chain can be modified using jumper P7 near JTAG header.

Following diagram shows JTAG chain configuration:

Tagus has automatic FMC detection using the PRSNT_M2C_L signal from FMC. Normally, when an FMC board is not connected, the Tagus’s onboard circuitry will automatically close the JTAG chain keeping FMC out from the chain, so no user intervention is required. But, still, jumper P7 has been provided as a redundant back up to close the JTAG chain in case the automatic circuitry doesn’t work due to non-compliant FMC modules connected to the Tagus, or any or unforeseen reasons.

FPGA startup configuration mode can be selected using switch S2.

Sliding it to ON puts FPGA in the “JTAG” configuration mode. Sliding it to OFF puts the FPGA to the “Master SPI” configuration mode.

PROG_B Button

Tagus features a Push-button S1 normally meant to be used as a “PROG_B” signal for configuration reset. Push-button S1 is connected to FPGA pin N12. For enabling manual configuration reset, push-button S1 connected to GND. The user can reconfigure the FPGA manually, by pressing this push-button S1.

“PROG_B” is an active-low input pin (pulled up with 4.7K external resistor) to the FPGA and it controls the configuration logic. When the PROG_B pin is de-asserted, resets the FPGA and initializes the new configuration.

Reset Button

Tagus features a Push-button S3 normally meant to be used as a “Reset” signal for designs running on FPGA. Push-button S3 is connected to FPGA pin P17. Push-button S3 is active-high. This pushbutton can also be used for any other input and is not just limited to be used as a Reset signal.

VADJ Power Supply for FMC Bank A is configurable via jumpers J2. The following are the jumper configurations for different voltages for the VADJ supply.

PCI Express 2.0 1-lane edge-connector on the Tagus can be used to interface with host PCs via PCI Express protocol. Each lane is capable of 5.0 GT/s resulting in a maximum theoretical data transfer rate of 500 MB/s for a single lane.

PCI Express x1 Edge Connector

Tagus features two SFP+ cages (Small form-factor hot-pluggable optical module transceivers), which can be used for optical fiber communication.

Tagus features a high speed, low pin-count FMC connector which can be used to provide additional features and capabilities to it using custom or commercial off-the-shelf daughter boards. Apart from IOs, 1 GTP lane is available via FMC connector for custom purposes.

FMC Banks C, D, G and H

This board requires a driver to be installed to use USB serial converter, for the board’s proper functioning when used with Windows. Ideally, Windows should automatically search and install the correct driver for the Tagus via Windows Update. For manual installation, the FTDI VCP drivers are available for download from http://www.ftdichip.com/.

The PCI Express specification requires cards to be ready for link training within 100 ms after the host PC’s power supply is stable.

The following constraints need to be added to the xdc file before synthesizing, implementing and generating a bitstream for a PCI Express design. These can be safely ignored if the PCI Express interface is not used in the design.

set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

Step 1: It is recommended to generate a .bin bitstream file along with .bit bitstream file. Click “Bitstream Settings”.

Step 2: Select the “-bin_file*” option in the dialog window and Click OK.

Step 3: Finally click “Generate Bitstream”.

Tagus Artix-7 PCI Express FPGA Board features an onboard JTAG connector that facilitates easy reprogramming of SRAM and onboard SPI flash through JTAG programmer like “Xilinx Platform cable USB”. The following steps illustrate how to program FPGA on the Tagus using JTAG.

Step1: By using JTAG cable, connect Xilinx platform cable USB to Tagus and power it up.

Step2: Open the Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step3: If the device is detected successfully, then select “Program Device” by right click on the target device “xc7a200t_0” as shown below.

Step4: In the dialog window which opens up, Vivado automatically chooses the correct bitstream file if the design was synthesized, implemented and bitstream generated successfully. If needed, browse to the bitstream which needs to be programmed to FPGA. Finally, click “Program”.

As soon as “Program” is clicked, a red-colored LED (D1) on the Tagus should light up, indicating that the programming process is going on. This LED will turn off when the configuration is complete.

A .bin or .mcs file is required for programming Tagus’s onboard QSPI flash.

Step 1: Open the Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 2: If the device is detected successfully, then select “Add Configuration Memory Device” by right click on the target device “xc7a200t_0” as shown below.

Step 3: Select the memory device “mt25ql128-spi-x1_x2_x4 (which is equivalent to n25q128-3.3v-spi-x1_x2_x4)”, then click OK.

Step 4: After completion of Step 3 the following dialog box will open. Click OK.

Step 5: Browse to the working .bin file or the .mcs file (whichever applicable) and click OK to program as shown below. If programming is successful, a confirmation message will be displayed.

Download Tagus Constraints for Vivado 

Tagus Schematics

Tagus FMC Easy Reference