Xilinx Spartan 6 FPGA Boards

Callisto S6 is an easy to use FPGA Development board featuring the Xilinx Spartan 6 FPGA with 2Gb DDR3 SDRAM. This board contains the Xilinx XC6SLX150– FGG676 FPGA. The high-speed USB 3.1 interface (USB-C connector) provides fast communication interface between FPGA and host PC. The Development board also provides easy access to JTAG signals on a standard Xilinx Platform Cable compatible header. Callisto S6 provides the user the flexibility of adding their own peripherals through IO Expansion Headers.

• FPGA: Spartan XC6SLX150 in FGG676 package
• DDR3: 2Gb DDR3 (MT41J128M16HA-125:K or equivalent)
• Flash memory: 128 Mb Quadbit SPI flash memory (N25Q128A13ESE40E)
• 2 x 100MHz CMOS oscillator
• USB 3.1 Gen1 @5Gbps (USB Type-C connector)
• JTAG header for programming and debugging.
• 12V DC power supply
• A Push Button for the reset pin
• 284 IOs for user-defined purposes
• Onboard voltage regulators for single power rail operation

• Signal Processing
• Product Prototype Development
• Communication devices development
• Educational tool for Schools and Universities
• Development and testing of custom embedded processors
• Accelerated Computing Integration

The following sections describe in detail how to use this module.

Along with the module, you may need the accessories listed below for easy and fast installation:

1. 12 V DC Power Supply.
2. USB A to USB-C cable (Optional).
3. A Xilinx Platform Cable USB II compatible JTAG programmer

This diagram should be used as a reference only. For detailed information, see Callisto S6’s schematics and mechanical dimensions at the end of this page. Details of individual connectors are as shown below.

This super speed USB 3.1 interface (USB-C connector) is used to help the host PC to communicate with the module at a very high speed (5Gbps). A USB-A to USB-C cable is used to connect the module to the host PC. It is primarily used to output debug information or as a console for the design running on the board. (the picture on the right shows USB-C connector).

By default, the board is configured to use +5V supply from USB. So an external power is not required unless USB port is unable to supply enough current. USB 3.1 ports are only capable of providing enough current for the module for small designs which require less power. The current requirement for this board largely depends on your application. Please consult FPGA data sheet for more details on power requirements. If for any reason, an external power supply needs to be used for the board, connect the DC power supply. Please refer to the marking on the board for more details. The external power supply should be in the range of +5 to +12V, with sufficient current rating.

Callisto S6 features a Push-button S1 normally meant to be used as “Reset” signal for designs running on FPGA. Push-button S1 is connected to FPGA pin A23. Push-button S1 is active-high. This pushbutton can also be used for any other input and is not just limited to be used as a Reset signal.

JTAG connector allows the FPGA’s JTAG registers to be accessed using a JTAG cable, compatible with Xilinx Platform Cable USB. Use this header, to attach JTAG cable for programming and debugging.

This device is equipped with a maximum of 284 user IO pins that can be used for various custom applications. All user IOs are length matched and can be used as differential pairs.

* These pins are from Bank 3 whose IOSTANDARD is LVCMOS15 (All other IOs has LVCMOS33 IOSTANDARD)

This product requires a driver to be installed for proper functioning when used with Windows. The D3XX driver can be downloaded from http://www.ftdichip.com/Drivers/D3XX.htm. Windows Users should download and run the latest WHQL Certified executable file that will prompt to install the FTDI CDM drivers.

HDL design needs to be converted to bitstream before it can be programmed to FPGA. Once the HDL is synthesized, it is easy to create a bit stream out of it. Please follow the steps below to generate bit stream from your design using ISE Web Pack.

Step 1: Right click on the “Generate Programming File” option in “Processes” window.

Step 2: Select “Process Properties” from the pop-up menu. In the dialog box, select “Create Binary Configuration File” and click “Apply”.

ise

Step 3: Click “OK” to close the dialog box. Right click on “Generate Programming File” option again and select “Run”. Now you will be able to find a “.bit” and a .bin files in the project directory and that file can be used for Callisto S6 configuration.

Callisto S6 is factory configured to be powered directly from USB port so make sure that you are using a USB port that can power the board properly. It is recommended to connect the board directly to the PC instead of using a hub. It is practically very difficult to estimate the power consumption of the board, as it depends heavily on your design and the clock used. XILINX provides tools to estimate the power consumption. In any case, if power from USB is not enough for your application, external supply can be applied to the board. Callisto S6 requires three different voltages, a 3.3V, a 1.8V supplies and a 1.2V supply. Onboard regulators derive these voltages from the USB/Ext power supply.

Callisto Spartan6 module features onboard JTAG connector which facilitates easy reprogramming of SRAM and on-board SPI flash through JTAG programmer like “XILINX Platform-cable usb”. Programming Callisto S6 using JTAG requires “XILINX ISE iMPACT” software which is bundled with XILINX ISE Design Suite. To program the SPI flash we need a “.mcs” file needs to be generated from the “.bit” file. Steps for generating “.mcs” file are as below. Programming FPGA SRAM does not require a “.mcs” file to be generated.

Generating “.mcs” file for Callisto S6

Step 1: Open ISE iMPACT. Click on “Create PROM file(PROM file formatter)”. In the dialog box, select “Configure Single FPGA” in storage device type. Then click on the green arrow on the right side.

Step 2: Select 128M in Storage Device (bits).Now click on “Add Storage Device”, then the green arrow on the right side.

Step 3: Set an output file name and the output file location (the “.mcs” file will be generated at this location which will be required later for programming the FPGA), then click OK twice, then select the “.bit” file we already generated then click Open and click NO when it prompts to add another device file.

Step 4: Double-click on “Generate File”. “Generate Succeeded” will be displayed as shown in fig below if the “.mcs” the file is generated successfully.

Step 1: Open ISE iMPACT. Click on “Boundary Scan” in the iMPACT flows window on the left top corner. Then right-click on the window panel on the right. Select “Initialize Chain”.

Step 2: If the device is detected properly you will get a pop-up window as shown below, Click OK. Then right-click on the SPI/BPI (next to the black arrow in the below fig.), select Add SPI/BPI Flash.

Step 3: Select the “.mcs” file we already created and click OK. Now choose “N25Q128” in the dialogue box appeared, then click OK.

Step 4: Click on “Flash”, Double Click on Program, select OK. If the programming is successful, a confirmation message will be displayed.

* All parameters considered nominal. Numato Systems Pvt Ltd reserves the right to modify products without notice.

Callisto S6 V2.0 Schematics

Download UCF constraints for ISE

Callisto S6 GPIO Easy Reference