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Aller AU-Plus FPGA Board with M.2 Interface

0 views April 7, 2025 megha-m 0

  1. Introduction
  2. Board Features
  3. Applications
  4. How to use Aller AU-Plus FPGA Module
    1. Hardware Accessories Required
    2. Connection Diagram
    3. Temperature and Heat Dissipation
    4. Power
    5. DDR4
    6. SPI FLASH
    7. Clock
    8. RGB LED
    9. M.2 Edge Connector
    10. Trusted Platform Module(TPM)
    11. FPC header (P1)
  5. Generating Bitstream for Aller AU-Plus FPGA Module
  6. Programming Aller AU-Plus FPGA Module
  7. Mechanical Dimensions
  8. Vivado XDC Constraints
  9. Schematics
  10. IO Length details

Introduction

The Aller AU-Plus FPGA Module is a high-performance development platform featuring an Artix Ultrascale+ FPGA, optimized for advanced computing and high-speed data processing. Equipped with an M.2 interface, SPI flash, DDR4 memory, and a TPM (Trusted Platform Module) for enhanced security, this board is ideal for applications requiring speed, security, and flexibility. The M.2 interface enables seamless integration with SSDs and other expansion modules, making it a versatile choice for embedded systems, data acquisition, and AI edge computing.

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Board Features

  • Device: AMD Artix Ultrascale+ FPGA (XCAU7P-1SBVC484I)
  • DDR4: 8Gb DDR4
  • x4 lane PCIe Gen3 (8 GT/s)
  • Onboard 512Mb QSPI flash memory for FPGA configuration
  • FPC header for programming and debugging
  • FPC header for GPIO’s.
  • 100 MHZ CMOS oscillator
  • 1 x Trusted Platform Module (AT97SC3205)
  • M.2 Connector Interface, M-Key
  • Powered from M.2 connector
  • 1 RGB LED for custom use
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Applications

  • High-Speed Data Acquisition and Processing
  • AI/ML Edge Computing
  • Signal Processing and Analysis
  • Memory Intensive FPGA development
  • Secure IoT Gateways (using TPM for enhanced security)
  • Network Acceleration and Traffic Management
  • Product Prototype Development
  • Cryptographic Applications and Secure Boot
  • Storage Solutions with M.2 SSDs
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How to use Aller AU-Plus FPGA Module

Hardware Accessories Required

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Connection Diagram

This diagram should be used as a reference only. The schematics are available at the end of this document for detailed information.

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Temperature and Heat Dissipation

M.2 form-factor doesn’t permit thick and large surface-area PCBs, so heat dissipation in M.2 profile modules is always a challenge. M.2 modules are traditionally used with application specific ICs for WiFi, USB etc, and the heat dissipation in those are comparatively lesser whereas in case of FPGAs, heat dissipation and power requirements are higher.

Aller AU-Plus FPGA module features an Artix Ultrascale+ SBVC484I FPGA with -1I speed grade (-40°C~100°C range) and 3200 MT/s DDR4 RAM. When running at maximum FPGA resource utilization and DDR4 running at max 3200 MT/s, huge amount of heat is dissipated. PCB thickness and surface area being low, the junction temperature of FPGA can rise to a high value. FPGA would get damaged if junction temperature rises above 100 °Celsius.

Therefore, heat sink is mandatory when using Aller AU-Plus module with heavy designs. Else, the FPGA and the board may get damaged. Heat sinks with good thermal coupling have been tested to decrease the temperatures by 15-20°C. If the temperature still approaches dangerous zone, then forced air cooling using fans might be required.

Aller AU-Plus module ships with a standard heat sink which should be sufficient for most use cases. It should be noted that with the addition of heat sink, the module may not fit inside some space constrained cases such as thin laptops. For simpler designs running at lower frequency and not using DDR4, the heat dissipation is less, and heat sink is not compulsorily required. It is expected that users do their own independent power analysis using AMD Power Estimator to find out the optimal cooling requirements for Aller AU-Plus module.

We recommend maintaining the junction temperature of FPGA below 70°C range. Users can use System Management Wizard block inside Artix Ultrascale+ FPGAs to measure temperature.

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Power

Aller AU-Plus FPGA module requires +3.3V power supply to function properly. It takes power from M.2 connector. Current requirement for this board largely depends on your application.

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DDR4

Aller AU-Plus FPGA Module uses DDR4 which is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. DDR4 is connected to the bank 66 of Aller AU-Plus FPGA module.

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SPI FLASH

The Aller AU-Plus FPGA Module has 512 Mbit of Quad SPI flash memory. It is a serial NOR flash which operates at the voltage of 1.8 V. It serves as the default primary boot device.

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Clock

Fabric Clock

Clock pins FPGA pins
REF_CLK_P K18
REF_CLK_NJ18

DDR4 Reference Clock

Clock pins FPGA pins
DDR4_REFCLK_P B14
DDR4_REFCLK_P B15
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RGB LED

Aller AU-Plus module features one RGB LED on the module which can be used for custom or debug purposes.

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M.2 Edge Connector

M.2 edge-connector on Aller AU-Plus module provides the power to the board. Each lane is capable of 8GT/s resulting in maximum theoretical data transfer rate of 4GB/s for all 4 lanes combined.

M.2 pin nameSignal nameFPGA Pins
REFCLK_PMGTREFCLK0P_124AA17
REFCLK_NMGTREFCLK0N_124AA18
M2_TX0_PMGTHTXP0_124AB19
M2_TX0_NMGTHTXN0_124AB20
M2_TX1_PMGTHTXP1_124Y19
M2_TX1_NMGTHTXN1_124Y20
M2_TX2_PMGTHTXP2_124V19
M2_TX2_NMGTHTXN2_124V20
M2_TX3_PMGTHTXP3_124T19
M2_TX3_NMGTHTXN3_124T20
M2_RX0_PMGTHRXP0_124AA21
M2_RX0_NMGTHRXN0_124AA22
M2_RX1_PMGTHRXP1_124W21
M2_RX1_NMGTHRXN1_124W22
M2_RX2_PMGTHRXP2_124U21
M2_RX2_NMGTHRXN2_124U22
M2_RX3_PMGTHRXP3_124R21
M2_RX3_NMGTHRXN3_124R22
M2_PERST#IO_L6N_HDGC_84AA6
M2_CLKREQ# IO_L7P_HDGC_84W8
M2_WAKE# IO_L6P_HDGC_84Y6
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Trusted Platform Module(TPM)

The Trusted Platform Module(TPM) is an integrated security module for hardware authentication. The security module is used primarily for cryptographic key generation, key storage and key management as well as generation and secure storage for digital certificates.

Signal NameSignal nameFPGA Pins
TPM_MOSIIO_L4N_AD12N_84AB8
TPM_MISOIO_L4P_AD12P_84AA8
TPM_CS#IO_L3N_AD13N_84Y9
TPM_CLK IO_L3P_AD13P_84Y10
TPM_RST# IO_L5P_HDGC_84AA7
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FPC header (P1)

The FPC header (P1) on the Module is used for FPGA programming and includes JTAG and UART pins.

The table lists all the pins on the FPC header (P1).

Pin no.FPC pin namesSignal nameFPGA pins
1VCC3V3
2PROGRAM_BPROGRAM_B_0C7
3FPGA_TMSTMS_0E8
4FPGA_TDITDI_0E10
5FPGA_TDOTDO_0D9
6FPGA_TCKTCK_0F8
7UART_RXIO_L12N_AD8N_84W6
8UART_TXIO_L12P_AD8P_84V6
9GND
10GND
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Generating Bitstream for Aller AU-Plus FPGA Module

The bitstream can be generated for Aller AU-Plus FPGA Module in Vivado by following the steps below:

Step 1: It is recommended to generate .bin bitstream file along with .bit bitstream file. Right Click on “Bitstream Settings”.

Step 2: Select “-bin_file*” option in the dialog window and Click “OK”.

Step 3: Finally click “Generate Bitstream”.

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Mechanical Dimensions

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Vivado XDC Constraints

Vivado XDC Constraints

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IO Length details

IO Length details

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