AMD Artix Ultrascale+ Boards

The Aller AU-Plus FPGA Module is a high-performance development platform featuring an Artix Ultrascale+ FPGA, optimized for advanced computing and high-speed data processing. Equipped with an M.2 interface, SPI flash, DDR4 memory, and a TPM (Trusted Platform Module) for enhanced security, this board is ideal for applications requiring speed, security, and flexibility. The M.2 interface enables seamless integration with SSDs and other expansion modules, making it a versatile choice for embedded systems, data acquisition, and AI edge computing.

• Device: AMD Artix Ultrascale+ FPGA (XCAU7P-1SBVC484I)
• DDR4: 8Gb DDR4
• x4 lane PCIe Gen3 (8 GT/s)
• Onboard 512Mb QSPI flash memory for FPGA configuration
• 100 MHZ CMOS oscillator
• 1 x Trusted Platform Module (AT97SC3205)
• M.2 Connector Interface, M-Key
• Powered from M.2 connector
• 1 RGB LED for custom use

The section below details how to work with the Aller AU-Plus module

• Aller AU-Plus FPGA Module.
• Aller Programmer.

This diagram should be used as a reference only. The schematics are available at the end of this document for detailed information.

M.2 form-factor doesn’t permit thick and large surface-area PCBs, so heat dissipation in M.2 profile modules is always a challenge. M.2 modules are traditionally used with application specific ICs for WiFi, USB etc, and the heat dissipation in those are comparatively lesser whereas in case of FPGAs, heat dissipation and power requirements are higher.

Aller AU-Plus FPGA module features an Artix Ultrascale+ SBVC484I FPGA with -1I speed grade (-40°C~100°C range) and 3200 MT/s DDR4 RAM. When running at maximum FPGA resource utilization and DDR4 running at max 3200 MT/s, huge amount of heat is dissipated. PCB thickness and surface area being low, the junction temperature of FPGA can rise to a high value. FPGA would get damaged if junction temperature rises above 100 °Celsius.

Therefore, heat sink is mandatory when using Aller AU-Plus module with heavy designs. Else, the FPGA and the board may get damaged. Heat sinks with good thermal coupling have been tested to decrease the temperatures by 15-20°C. If the temperature still approaches dangerous zone, then forced air cooling using fans might be required.

Aller AU-Plus module ships with a standard heat sink which should be sufficient for most use cases. It should be noted that with the addition of heat sink, the module may not fit inside some space constrained cases such as thin laptops. For simpler designs running at lower frequency and not using DDR4, the heat dissipation is less, and heat sink is not compulsorily required. It is expected that users do their own independent power analysis using AMD Power Estimator to find out the optimal cooling requirements for Aller AU-Plus module.

We recommend maintaining the junction temperature of FPGA below 70°C range. Users can use System Management Wizard block inside Artix Ultrascale+ FPGAs to measure temperature.

Aller AU-Plus FPGA module requires +3.3V power supply to function properly. It takes power from M.2 connector. Current requirement for this board largely depends on your application.

Aller AU-Plus FPGA Module uses DDR4 which is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. DDR4 is connected to the bank 66 of Aller AU-Plus FPGA module.

The Aller AU-Plus FPGA Module has 512 Mbit of Quad SPI flash memory. It is a serial NOR flash which operates at the voltage of 1.8 V. It serves as the default primary boot device.

Fabric Clock

DDR4 Reference Clock

Aller AU-Plus module features one RGB LED on the module which can be used for custom or debug purposes.

M.2 edge-connector on Aller AU-Plus module provides the power to the board. Each lane is capable of 8GT/s resulting in maximum theoretical data transfer rate of 4GB/s for all 4 lanes combined.

The Trusted Platform Module(TPM) is an integrated security module for hardware authentication. The security module is used primarily for cryptographic key generation, key storage and key management as well as generation and secure storage for digital certificates.

The bitstream can be generated for Aller AU-Plus FPGA Module in Vivado by following the steps below:

Step 1: It is recommended to generate .bin bitstream file along with .bit bitstream file. Right Click on “Bitstream Settings”.

Step 2: Select “-bin_file*” option in the dialog window and Click “OK”.

Step 3: Finally click “Generate Bitstream”.

Please refer to the Aller Programmer User Manual for setup and programming steps.

Vivado XDC Constraints

Aller AU Plus module schematic

IO Length details