Xilinx Zynq FPGA Boards

TityraCore Z7 SODIMM FPGA

0 views May 17, 2023 milna-ms 0

Introduction

 

TityraCore Z7 SODIMM incorporates the AMD Zynq XC7Z020 chip, which seamlessly integrates programmable logic with a dual-core ARM Cortex-A9 processor. This integration provides a potent blend of hardware and software processing capabilities, all within a single chip. Zynq series feature a hard System on Chip (SoC) with an ARM core and the range of peripherals offered includes an extensive array of functionalities, such as UARTs, Ethernet controllers, USB ports, timers, interrupt controllers, and various other features. It has a seamless integration of the Processing System(PS) with the Programmable Logic (PL) in which the interaction between them is enabled by a high-bandwidth interface, ensuring communication and efficient data transfer between them. TityraCore Z7 SODIMM is specifically designed for the development and integration of FPGA based accelerated features into other larger designs. It opens up a vast realm of possibilities for implementing innovative solutions across a wide range of applications.

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Board Features

  • Device: XC7Z020 in CLG484 package, Speed Grade: -1
  • SDRAM: 4 Gb DDR3L (MT41K256M16TW-107 IT:P TR or equivalent)
  • Flash memory: 1 Gb Quad bit SPI flash memory (MT25QL01GBBB8E12)
  • 33 MHz CMOS oscillator
  • 50 MHz CMOS oscillator
  • Gigabit Ethernet, Real Time Clock, Trusted Platform Module, MAC ID
  • High-Speed USB 2.0 OTG interface.
  • Flash programming via JTAG and USB
  • Micro SD card slot for memory expansion
  • 8 GB eMMC
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Applications

  • Product Prototype Development
  • Accelerated computing integration
  • Custom Embedded platform
  • Signal Processing
  • Communication devices development
  • Educational tool for Schools and Universities
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Connection Diagram

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Reference clock

BankPin No.Signal NameFunction
500F7PS_CLK_50033.33 MHz CLK
34B19IO_L13P_T2_MRCC_3550 MHz CLK
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Reset

BankPin No.Signal nameFunction
501C9PS_SRST_B_501n RST IN
500B5PS_POR_B_500Program B
Yes No Suggest edit

DDR3L SDRAM

TityraCore SODIMM includes DDR3L memory technology which is the third generation of DDR memory technology designed to operate at lower voltage levels (1.35 V) compared to standard DDR3 modules. TityraCore SODIMM uses micron MT41K256M16TW-107 IT:P TR memory which has a capacity of  4 Gb of RAM. DDR3L is connected to PS section of Zynq-7000 AP SoC and has the speed up to 1866 MT/s.

BankPin No.Signal NameFunction
502D1PS_DDR_DQ0_502DDR-DQ0
502C3PS_DDR_DQ1_502DDR-DQ1
502B2PS_DDR_DQ2_502DDR-DQ2
502D3PS_DDR_DQ3_502DDR-DQ3
502E3PS_DDR_DQ4_502DDR-DQ4
502E1PS_DDR_DQ5_502DDR-DQ5
502F2PS_DDR_DQ6_502DDR-DQ6
502F1PS_DDR_DQ7_502DDR-DQ7
502G2PS_DDR_DQ8_502DDR-DQ8
502G1PS_DDR_DQ9_502DDR-DQ9
502L1PS_DDR_DQ10_502DDR-DQ10
502L2PS_DDR_DQ11_502DDR-DQ11
502L3PS_DDR_DQ12_502DDR-DQ12
502K1PS_DDR_DQ13_502DDR-DQ13
502J1PS_DDR_DQ14_502DDR-DQ14
502K3PS_DDR_DQ15_502DDR-DQ15
502M4PS_DDR_A0_502DDR0-A0
502M5PS_DDR_A1_502DDR0-A1
502K4PS_DDR_A2_502DDR0-A2
502L4PS_DDR_A3_502DDR0-A3
502K6PS_DDR_A4_502DDR0-A4
502K5PS_DDR_A5_502DDR0-A5
502J7PS_DDR_A6_502DDR0-A6
502J6PS_DDR_A7_502DDR0-A7
502J5PS_DDR_A8_502DDR0-A8
502H5PS_DDR_A9_502DDR0-A9
502J3PS_DDR_A10_502DDR0-A10
502G5PS_DDR_A11_502DDR0-A11
502H4PS_DDR_A12_502DDR0-A12
502F4PS_DDR_A13_502DDR0-A13
502G4PS_DDR_A14_502DDR0-A14
502L7PS_DDR_BA0_502DDR-BA0
502L6PS_DDR_BA1_502DDR-BA1
502M6PS_DDR_BA2_502DDR-BA2
502P6PS_DDR_CS_B_502DDR0-CS#
502R5PS_DDR_RAS_B_502DDR0-RAS
502P3PS_DDR_CAS_B_502DDR0-CAS
502R4PS_DDR_WE_B_502DDR0-WE
502N5PS_DDR_CKN_502DDR0-CK N
502N4PS_DDR_CKP_502DDR0-CK P
502V3PS_DDR_CKE_502DDR0-CKE
502F3PS_DDR_DRST_B_502DDR0-RESET
502P5PS_DDR_ODT_502DDR0-ODT
502B1PS_DDR_DM0_502DDR-DM0
502H3PS_DDR_DM1_502DDR-DM1
502C2PS_DDR_DQS_P0_502DDR_DQS0 P
502D2PS_DDR_DQS_N0_502DDR_DQS0 N
502H2PS_DDR_DQS_P1_502DDR_DQS1 P
502J2PS_DDR_DQS_N1_502DDR_DQS1 N
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QSPI Flash

The TityraCore SODIMM has 1 Gb of Quad bit SPI flash memory. It is a serial NOR flash which operates at the voltage of 3.3 V. It is connected to QSPI controller of the PS and serves as the default primary boot device. Memory size of QSPI flash memory can be expanded to 8GB using eMMC flash.

BankPin No.Signal NameFunction
500A1
PS_MIO1_500SPI_CS_N
500A2
PS_MIO2_500SPI_DQ[0]
500F6PS_MIO3_500SPI_DQ[1]
500E4PS_MIO4_500SPI_DQ[2]
500A3PS_MIO5_500SPI_DQ[3]
500A4PS_MIO6_500SPI_SCK
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Micro SD Card

The TityrCore SODIMM have micro-SD card feature that can be incorporated in the carrier board. SD Card can be used to store non-volatile external memory. It is directly connected to the SD0 controller of the PS MIO bank  and operates at 1.8 V.

BankPin No.Signal NameFunction
501E14PS_MIO40_501SD0_CLK
501C8PS_MIO41_501SD0_CMD
501D8PS_MIO42_501SD0_DAT0
501B11PS_MIO43_501SD0_DAT1
501E13PS_MIO44_501SD0_DAT2
501B9PS_MIO45_501SD0_DAT3
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eMMC Flash

TityraCore SODIMM supports 8 Gb of eMMC flash memory for additional storage. It operates at a voltage level of 3.3 V and is connected to sd1 controller of the PS MIO bank . It can serve as a means to increase the capacity of SPI flash memory and function as a secondary boot device.

BankPin No.Signal NameFunction
500G7PS_MIO10_500eMMC_DAT0
500B4PS_MIO11_500eMMC_CMD
500C5PS_MIO12_500eMMC_CLK
500A6PS_MIO13_500eMMC_DAT1
500B6PS_MIO14_500eMMC_DAT2
500E6PS_MIO15_500eMMC_DAT3
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Ethernet

TityraCore SODIMM implements single-Chip 10/100/1000 Mbps Ethernet Transceiver, with 1.8 V IO operating voltage using Gigabit ethernet PHY “KSZ9031RNX”. It provides the Reduced Gigabit Media Independent Interface (RGMII) and is connected to the Gigabit Ethernet controller of PS MIO bank in Zynq-7000 AP SOC.

BankPin No.Signal NameFunction
501D6PS_MIO16_501ETH_TXCLK
501E9PS_MIO17_501ETH_TXD0
501A7PS_MIO18_501ETH_TXD1
501E10PS_MIO19_501ETH_TXD2
501A8PS_MIO20_501ETH_TXD3
501F11PS_MIO21_501ETH_TXCTL
501A14PS_MIO22_501ETH_RXCLK
501E11PS_MIO23_501ETH_RXD0
501B7PS_MIO24_501ETH_RXD1
501F12PS_MIO25_501ETH_RXD2
501A13PS_MIO26_501ETH_RXD3
501D7PS_MIO27_501ETH_RXCTL
501D10PS_MIO52_501ETH_MDC
501C12PS_MIO53_501ETH_MDIO
Yes No Suggest edit

USB 2.0 OTG

TityraCore SODIMM support high speed USB 2.0 On-The-Go (OTG) transceiver with 24 MHz operating frequency. TityraCore SODIMM uses “USB3320” ULPI transceiver and supports both device and host modes. The ULPI (UTMI+ Low Pin Interface) protocol is utilized to establish a connection between MIO (Multi-Function Input/Output) pins and the PHY (Physical Layer) component. It is connected to the OTG controller of PS MIO bank and works at 1.8V voltage.

BankPin No.Signal NameFunction
501A12PS_MIO28_501USB_D4
501E8PS_MIO29_501USB_DIR
501A11PS_MIO30_501USB_STP
501F9PS_MIO31_501USB_NXT
501C7PS_MIO32_501USB_D0
501G13PS_MIO33_501USB_D1
501B12PS_MIO34_501USB_D2
501F14PS_MIO35_501USB_D3
501A9PS_MIO36_501USB_CLK
501B14PS_MIO37_501USB_D5
501F13PS_MIO38_501USB_D6
501C13PS_MIO39_501USB_D7
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Trusted Platform Module

The Trusted Platform Module(TPM) is an integrated security module for hardware authentication. The security module is used primarily for cryptographic key generation, key storage and key management as well as generation and secure storage for digital certificates.

BankPin No.Signal NameFunction
33W16IO_L14P_T2_SRCC_33TPM_CLK
33Y16IO_L14N_T2_SRCC_33TPM_CS#
33U15IO_L15P_T2_DQS_33TPM_RST#
33U16IO_L15N_T2_DQS_33TPM_MISO
33U17IO_L16P_T2_33TPM_MOSI
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Real Time Clock

TityraCore SODIMM includes Real Time Clock (RTC), an integral part of electronic devices that operates independently of the device to accurately track real-world time. It is connected to PL Bank33 and has an operating voltage of 3.3 V.

BankPin No.Signal NameFunction
34W17IO_L13P_T2_MRCC_33RT_SCL
34W18IO_L13N_T2_MRCC_33RT_SDA
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MAC EEPROM

TityraCore SODIMM features MAC ID EEPROM, which is a memory chip that stores the unique MAC address of a network interface. It is a non-volatile memory that interfaces with PL Bank13 of Zynq-7000 AP SoC.  It operates at a voltage of 3.3 V.

BankPin No.Signal NameFunction
13V7IO_L23P_T3_13MAC_SCL
13W7IO_L23N_T3_13MAC_SDA
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UART

TityraCore SODIMM have UART interface connected to PS UART controller peripheral of the device. UART offer a flexible and user-friendly solution for incorporating serial communication interfaces, facilitating seamless data exchange with external devices across a diverse array of applications.

BankPin No.Signal NameFunction
501D13PS_MIO50_501UART_RX
501C10PS_MIO51_501UART_TX
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I2C

TityraCore SODIMM offers I2C communication through PS I2C controller and offers a flexible and efficient solution for establishing communication with various peripheral devices using the I2C protocol. It has a operating voltage of 1.8 V.

BankPin No.Signal NameFunction
501D12PS_MIO46_501I2C_SCL
501B10PS_MIO47_501I2C_SDA
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Header P1

BankPin NoSignal namefunction
35G17IO_L6P_T0_35P1_1
13U9IO_L6N_T0_VREF_13P1_2
35F17IO_L6N_T0_VREF_35P1_3
34P15IO_L19N_T3_VREF_34P1_4
35H19IO_L19P_T3_35P1_5
35H20IO_L19N_T3_VREF_35P1_6
34H15IO_0_34P1_7
34L16IO_L3N_T0_DQS_34P1_8
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Header P2

BankPin NoSignal NameFunction
34N15IO_L19P_T3_34P2_1
34M20IO_L13N_T2_MRCC_34P2_2
35D22IO_L16P_T2_35P2_3
35C22IO_L16N_T2_35P2_4
34R15IO_25_34P2_5
34R16IO_L24N_T3_34P2_6
34M15IO_L6P_T0_34P2_7
34M16IO_L6N_T0_VREF_34P2_8
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GPIO

BankPin No.Signal Name
13AA9PL_IO_L11_T1_SRCC_13_P
13AA8PL_IO_L11_T1_SRCC_13_N
13Y9PL_IO_L12_T1_MRCC_13_P
13Y8PL_IO_L12_T1_MRCC_13_N
13Y6PL_IO_L13_T2_MRCC_13_P
13Y5PL_IO_L13_T2_MRCC_13_N
13AA7PL_IO_L14_T2_SRCC_13_P
13AA6PL_IO_L14_T2_SRCC_13_N
13AB2PL_IO_L15_T2_DQS_13_P
13AB1PL_IO_L15_T2_DQS_13_N
13AB5PL_IO_L16_T2_13_P
13AB4PL_IO_L16_T2_13_N
13AB7PL_IO_L17_T2_13_P
13AB6PL_IO_L17_T2_13_N
13Y4PL_IO_L18_T2_13_P
13AA4PL_IO_L18_T2_13_N
13R6PL_IO_L19_T3_13_P
13T6PL_IO_L19_T3_13_N
13T4PL_IO_L20_T3_13_P
13U4PL_IO_L20_T3_13_N
13V5PL_IO_L21_T3_DQS_13_P
13V4PL_IO_L21_T3_DQS_13_N
13U6PL_IO_L22_T3_13_P
13U5PL_IO_L22_T3_13_N
34J15PL_IO_L1_T0_34_P
34K15PL_IO_L1_T0_34_N
34J16PL_IO_L2_T0_34_P
34J17PL_IO_L2_T0_34_N
34L17PL_IO_L4_T0_34_P
34M17PL_IO_L4_T0_34_N
34N17PL_IO_L5_T0_34_P
34N18PL_IO_L5_T0_34_N
34J18PL_IO_L7_T1_34_P
34K18PL_IO_L7_T1_34_N
34J21PL_IO_L8_T1_34_P
34J22PL_IO_L8_T1_34_N
34J20PL_IO_L9_T1_DQS_34_P
34K21PL_IO_L9_T1_DQS_34_N
34L21PL_IO_L10_T1_34_P
34L22PL_IO_L10_T1_34_N
34K19PL_IO_L11_T1_SRCC_34_P
34K20PL_IO_L11_T1_SRCC_34_N
34L18PL_IO_L12_T1_MRCC_34_P
34L19PL_IO_L12_T1_MRCC_34_N
34N19PL_IO_L14_T2_SRCC_34_P
34N20PL_IO_L14_T2_SRCC_34_N
34M21PL_IO_L15_T2_DQS_34_P
34M22PL_IO_L15_T2_DQS_34_N
34N22PL_IO_L16_T2_34_P
34P22PL_IO_L16_T2_34_N
34R20PL_IO_L17_T2_34_P
34R21PL_IO_L17_T2_34_N
34P20PL_IO_L18_T2_34_P
34P21PL_IO_L18_T2_34_N
34P17PL_IO_L20_T3_34_P
34P18PL_IO_L20_T3_34_N
34T16PL_IO_L21_T3_DQS_34_P
34T17PL_IO_L21_T3_DQS_34_N
34R19PL_IO_L22_T3_34_P
34T19PL_IO_L22_T3_34_N
34R18PL_IO_L23_T3_34_P
34T18PL_IO_L23_T3_34_N
35H17PL_IO_0_35
35F16PL_IO_L1_T0_AD0_35_P
35E16PL_IO_L1_T0_AD0_35_N
35D16PL_IO_L2_T0_AD8_35_P
35D17PL_IO_L2_T0_AD8_35_N
35E15PL_IO_L3_T0_DQS_AD1_35_P
35D15PL_IO_L3_T0_DQS_AD1_35_N
35G15PL_IO_L4_T0_35_P
35G16PL_IO_L4_T0_35_N
35F18PL_IO_L5_T0_AD9_35_P
35E18PL_IO_L5_T0_AD9_35_N
35C15PL_IO_L7_T1_AD2_35_P
35B15PL_IO_L7_T1_AD2_35_N
35B16PL_IO_L8_T1_AD10_35_P
35B17PL_IO_L8_T1_AD10_35_N
35A16PL_IO_L9_T1_DQS_AD3_35_P
35A17PL_IO_L9_T1_DQS_AD3_35_N
35A18PL_IO_L10_T1_AD11_35_P
35A19PL_IO_L10_T1_AD11_35_N
35C17PL_IO_L11_T1_SRCC_35_P
35C18PL_IO_L11_T1_SRCC_35_N
35D18PL_IO_L12_T1_MRCC_35_P
35C19PL_IO_L12_T1_MRCC_35_N
35D20PL_IO_L14_T2_AD4_SRCC_35_P
35C20PL_IO_L14_T2_AD4_SRCC_35_N
35A21PL_IO_L15_T2_DQS_AD12_35_P
35A22PL_IO_L15_T2_DQS_AD12_35_N
35E21PL_IO_L17_T2_AD5_35_P
35D21PL_IO_L17_T2_AD5_35_N
35B21PL_IO_L18_T2_AD13_35_P
35B22PL_IO_L18_T2_AD13_35_N
35G19PL_IO_L20_T3_AD6_35_P
35F19PL_IO_L20_T3_AD6_35_N
35E19PL_IO_L21_T3_DQS_AD14_35_P
35E20PL_IO_L21_T3_DQS_AD14_35_N
35G20PL_IO_L22_T3_AD7_35_P
35G21PL_IO_L22_T3_AD7_35_N
35F21PL_IO_L23_T3_35_P
35F22PL_IO_L23_T3_35_N
35H22PL_IO_L24_T3_AD15_35_P
35G22PL_IO_L24_T3_AD15_35_N
35H18PL_IO_25_35
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Technical Specifications

Parameter *ValueUnit
Basic Specifications
Number of GPIOs106
On-board oscillator frequency33.33MHz
On-board oscillator frequency (ASEM1-50.000MHZ-LC-T)50MHz
DDR3L Capacity4Gb
Quad SPI Flash Memory (MT25QL01GBBB8E12)1Gb
Power supply voltage (External)5, 3.3V
Internal Processor Core Voltage1.0V
Auxiliary supply voltage relative to GND1.8V
Output drivers supply voltage relative to GND-0.5 to 3.6V
PS MIO I/O supply voltage (VCCO_MIO)1.8, 3.3V
PS MIO I/O input voltage1.8, 3.3V
PS DDR I/O input voltage1.35 or 1.5 V
Maximum Processor Frequency667MHz

* All parameters considered nominal. Numato Systems Pvt Ltd reserves the right to modify products without notice.

Yes No Suggest edit

SODIMM PCB Edge Connector Pinout Map

SignalSODIMM Pin (Top)SODIMM Pin (Bottom)Signal
GND12GPHY_ATXRX_N
NC34GPHY_ATXRX_P
GND56GPHY_BTXRX_N
PL_IO_L18_T2_13_N78GPHY_BTXRX_P
PL_IO_L18_T2_13_P910P1_2
GPHY_LINK_LED21112GPHY_ACTIVITY_LED1
GND1314GPHY_CTXRX_N
GPHY_DTXRX_N1516GPHY_CTXRX_P
GPHY_DTXRX_P1718PL_IO_L11_T1_SRCC_13_N
PL_IO_L11_T1_SRCC_13_P1920VCC_3V3
PL_IO_L21_T3_DQS_13_P2122PL_IO_L22_T3_13_P
PL_IO_L21_T3_DQS_13_N2324PL_IO_L22_T3_13_N
NC2526PL_IO_L14_T2_SRCC_13_P
GND2728PL_IO_L14_T2_SRCC_13_N
PL_IO_L19_T3_13_P2930PL_IO_L20_T3_13_P
PL_IO_L19_T3_13_N3132VCC_3V3
PL_IO_L20_T3_13_N3334PL_IO_L1_T0_34_N
PL_IO_L2_T0_34_N3536PL_IO_L1_T0_34_P
PL_IO_L2_T0_34_P3738PL_IO_L7_T1_34_N
PL_IO_L7_T1_34_P3940GND
GND4142PL_IO_L20_T3_34_N
PL_IO_L4_T0_34_N4344PL_IO_L20_T3_34_P
PL_IO_L4_T0_34_P4546VCC_3V3
P2_24748PL_IO_L15_T2_DQS_13_N
NC4950PL_IO_L15_T2_DQS_13_P
GND5152PL_IO_L13_T2_MRCC_13_N
PL_IO_L12_T1_MRCC_13_N5354PL_IO_L13_T2_MRCC_13_P
PL_IO_L12_T1_MRCC_13_P5556PL_IO_L16_T2_13_N
PL_IO_L17_T2_13_N5758PL_IO_L16_T2_13_P
PL_IO_L17_T2_13_P5960VCC_3V3
PL_IO_L21_T3_DQS_34_N6162PL_IO_L23_T3_34_N
PL_IO_L21_T3_DQS_34_P6364PL_IO_L23_T3_34_P
GND6566PL_IO_L9_T1_DQS_34_N
PL_IO_L14_T2_SRCC_34_N6768PL_IO_L9_T1_DQS_34_P
PL_IO_L14_T2_SRCC_34_P6970PL_IO_L22_T3_34_P
P2_87172VCC_3V3
P2_77374PL_IO_L22_T3_34_N
P1_77576P2_5
USB_OTG_ID7778USB_PWR_EN
GND7980PL_IO_L3P_T0_DQS_PUDC_B_34
USB_OTG_DP8182NC
USB_OTG_DN8384PROGRAM B
NC8586PL_IO_L16_T2_34_P
NC8788VIN_3V3
PL_IO_L16_T2_34_N8990PL_IO_L12_T1_MRCC_34_P
P2_19192PL_IO_L12_T1_MRCC_34_N
P1_49394PL_IO_L15_T2_DQS_34_P
GND9596PL_IO_L15_T2_DQS_34_N
PL_IO_L17_T2_34_P9798PL_IO_L5_T0_34_P
PL_IO_L17_T2_34_N99100PL_IO_L5_T0_34_N
PL_IO_L18_T2_34_P101102PL_IO_L10_T1_34_P
PL_IO_L18_T2_34_N103104PL_IO_L10_T1_34_N
GPIO48_PS_MIO48_501105106VCC_3V3
SD0_DATA0(PS_MIO42_501)107108SD0_CMD(PS_MIO41_501)
SD0_CLK(PS_MIO40_501)109110P2_6
SD0_DATA1(PS_MIO43_501)111112SD0_DATA2(PS_MIO44_501)
GND113114SD0_DATA3(PS_MIO45_501)
I2C0_SDA(PS_MIO47_501)115116I2C0_SCL(PS_MIO46_501)
UART0_RX(PS_MIO50_501)117118UART0_TX(PS_MIO51_501)
PL_IO_L11_T1_SRCC_34_N119120PL_IO_L8_T1_34_N
PL_IO_L11_T1_SRCC_34_P121122PL_IO_L8_T1_34_P
P1_8123124VCC_3V3
PL_IO_L4_T0_35_P125126PL_IO_L3_T0_DQS_AD1_35_P
NC127128NC
NC129130NC
GND131132PL_IO_L1_T0_AD0_35_N
PL_IO_L4_T0_35_N133134PL_IO_L7_T1_AD2_35_P
NC135136PL_IO_L11_T1_SRCC_35_P
NC137138PL_IO_L1_T0_AD0_35_P
PL_IO_L22_T3_AD7_35_P139140PL_IO_L3_T0_DQS_AD1_35_N
NC141142VCC_3V3
PL_IO_L20_T3_AD6_35_N143144PL_IO_L11_T1_SRCC_35_N
PL_IO_L20_T3_AD6_35_P145146PL_IO_L5_T0_AD9_35_P
PL_IO_L5_T0_AD9_35_N147148PL_IO_L24_T3_AD15_35_P
PL_IO_L24_T3_AD15_35_N149150PL_IO_L12_T1_MRCC_35_P
GND151152PL_IO_L14P_T2_AD4_SRCC_35_P
PL_IO_L8_T1_AD10_35_N153154PL_IO_L8_T1_AD10_35_P
P1_3155156P2_3
PL_IO_25_35157158PL_IO_L12_T1_MRCC_35_N
PL_IO_L14N_T2_AD4_SRCC_35_N159160VCC_3V3
P1_1161162PL_IO_L21_T3_DQS_AD14_35_P
PL_IO_L22_T3_AD7_35_N163164PL_IO_L21_T3_DQS_AD14_35_N
PL_IO_L15_T2_DQS_AD12_35_N165166PL_IO_L7_T1_AD2_35_N
P1_5167168P2_4
GND169170PL_IO_L2_T0_AD8_35_P
PL_IO_L15_T2_DQS_AD12_35_P171172PL_IO_L2_T0_AD8_35_N
P1_6173174PL_IO_L17_T2_AD5_35_P
PL_IO_L18_T2_AD13_35_P175176PL_IO_L23_T3_35_P
PL_IO_L10_T1_AD11_35_N177178PL_IO_L23_T3_35_N
PL_IO_L18_T2_AD13_35_N179180VCC_3V3
PL_IO_L10_T1_AD11_35_P181182NC
VRTC183184SPI_DQ3
GND185186GND
n_RST_IN187188NC
PL_IO_L17_T2_AD5_35_N189190PL_IO_L9_T1_DQS_AD3_35_N
JTAG_TDO191192VCC_3V3
NC193194PL_IO_0_35
JTAG_TDI195196PL_IO_L9_T1_DQS_AD3_35_P
JTAG_TCK197198GND
JTAG_TMS199200VDD5V
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