Introduction
TityraCore Z7 SoC SoDIMM incorporates the AMD Zynq XC7Z020 chip, seamlessly integrating programmable logic with a dual-core ARM Cortex-A9 processor. This integration provides a potent blend of hardware and software processing capabilities, all within a single chip. Zynq series features a hard System on Chip (SoC) with an ARM core. The range of peripherals offered includes an extensive array of functionalities, such as UARTs, Ethernet controllers, USB ports, timers, interrupt controllers, and various other features. It has a seamless integration of the Processing System(PS) with the Programmable Logic (PL) in which the interaction between them is enabled by a high-bandwidth interface, ensuring communication and efficient data transfer between them. TityraCore Z7 SoC SoDIMM is specifically designed for the development and integration of FPGA-based accelerated features into other larger designs. It opens up a vast realm of possibilities for implementing innovative solutions across various applications.
Board features
- Device: XC7Z020 in CLG484 package, Speed Grade: -1
- SDRAM: 2 GB DDR3L (MT41K256M16TW-107 IT:P TR or equivalent)
- Flash memory: 128 Mb Quad bit SPI flash memory (N25Q128A13EF840E)
- 33 MHz CMOS oscillator
- 50 MHz CMOS oscillator
- Gigabit Ethernet, Real Time Clock, CAN BUS, MAC ID
- MIPI interfacing
- High-Speed USB 2.0 OTG interface.
- JTAG and USB programming
- Micro SD card for memory expansion
- 8 Gb eMMC
Application
- Product Prototype Development
- Accelerated computing integration
- Custom Embedded platform
- Signal Processing
- Communication devices development
- Educational tool for Schools and Universities
Components/Tools required
Along with the module, you may need the items in the list below for easy and fast installation.
- Carrier board
- Micro-B cable.
- USB-C cable
- A Xilinx Platform Cable USB II compatible JTAG programmer
- DC Power supply
Connection Diagram
Reference clock
Bank Pin No. Signal Name Function
500 F7 PS_CLK_500 33.33 MHz CLK
34 B19 IO_L13P_T2_MRCC_35 50 MHz CLK
Reset
Bank Pin No. Signal name Function
501 C9 PS_SRST_B_501 n RST IN
500 B5 PS_POR_B_500 Program B
DDR3L SDRAM
TityraCore Z7 SoC SoDIMM includes DDR3L memory technology which is the third generation of DDR memory technology designed to operate at lower voltage levels (1.35 V) compared to standard DDR3 modules. TityraCore Z7 SoC SoDIMM uses micron MT41K256M16TW-107 IT:P TR memory which has a capacity of 2 GB of RAM.
Bank Pin No. Signal Name Function
502 D1 PS_DDR_DQ0_502 DDR-DQ0
502 C3 PS_DDR_DQ1_502 DDR-DQ1
502 B2 PS_DDR_DQ2_502 DDR-DQ2
502 D3 PS_DDR_DQ3_502 DDR-DQ3
502 E3 PS_DDR_DQ4_502 DDR-DQ4
502 E1 PS_DDR_DQ5_502 DDR-DQ5
502 F2 PS_DDR_DQ6_502 DDR-DQ6
502 F1 PS_DDR_DQ7_502 DDR-DQ7
502 G2 PS_DDR_DQ8_502 DDR-DQ8
502 G1 PS_DDR_DQ9_502 DDR-DQ9
502 L1 PS_DDR_DQ10_502 DDR-DQ10
502 L2 PS_DDR_DQ11_502 DDR-DQ11
502 L3 PS_DDR_DQ12_502 DDR-DQ12
502 K1 PS_DDR_DQ13_502 DDR-DQ13
502 J1 PS_DDR_DQ14_502 DDR-DQ14
502 K3 PS_DDR_DQ15_502 DDR-DQ15
502 M1 PS_DDR_DQ16_502 DDR-DQ16
502 T3 PS_DDR_DQ17_502 DDR-DQ17
502 N3 PS_DDR_DQ18_502 DDR-DQ18
502 T1 PS_DDR_DQ19_502 DDR-DQ19
502 R3 PS_DDR_DQ20_502 DDR-D20
502 T2 PS_DDR_DQ21_502 DDR-DQ21
502 M2 PS_DDR_DQ22_502 DDR-DQ22
502 R1 PS_DDR_DQ23_502 DDR-DQ23
502 AA3 PS_DDR_DQ24_502 DDR-DQ24
502 U1 PS_DDR_DQ25_502 DDR-DQ25
502 AA1 PS_DDR_DQ26_502 DDR-DQ26
502 U2 PS_DDR_DQ27_502 DDR-DQ27
502 W1 PS_DDR_DQ28_502 DDR-DQ28
502 Y3 PS_DDR_DQ29_502 DDR-DQ29
502 W3 PS_DDR_DQ30_502 DDR-DQ30
502 Y1 PS_DDR_DQ31_502 DDR-DQ31
502 M4 PS_DDR_A0_502 DDR0-A0
502 M5 PS_DDR_A1_502 DDR0-A1
502 K4 PS_DDR_A2_502 DDR0-A2
502 L4 PS_DDR_A3_502 DDR0-A3
502 K6 PS_DDR_A4_502 DDR0-A4
502 K5 PS_DDR_A5_502 DDR0-A5
502 J7 PS_DDR_A6_502 DDR0-A6
502 J6 PS_DDR_A7_502 DDR0-A7
502 J5 PS_DDR_A8_502 DDR0-A8
502 H5 PS_DDR_A9_502 DDR0-A9
502 J3 PS_DDR_A10_502 DDR0-A10
502 G5 PS_DDR_A11_502 DDR0-A11
502 H4 PS_DDR_A12_502 DDR0-A12
502 F4 PS_DDR_A13_502 DDR0-A13
502 G4 PS_DDR_A14_502 DDR0-A14
502 L7 PS_DDR_BA0_502 DDR-BA0
502 L6 PS_DDR_BA1_502 DDR-BA1
502 M6 PS_DDR_BA2_502 DDR-BA2
502 P6 PS_DDR_CS_B_502 DDR0-CS#
502 R5 PS_DDR_RAS_B_502 DDR0-RAS
502 P3 PS_DDR_CAS_B_502 DDR0-CAS
502 R4 PS_DDR_WE_B_502 DDR0-WE
502 N5 PS_DDR_CKN_502 DDR0-CK N
502 N4 PS_DDR_CKP_502 DDR0-CK P
502 V3 PS_DDR_CKE_502 DDR0-CKE
502 F3 PS_DDR_DRST_B_502 DDR0-RESET
502 P5 PS_DDR_ODT_502 DDR0-ODT
502 B1 PS_DDR_DM0_502 DDR-DM0
502 H3 PS_DDR_DM1_502 DDR-DM1
502 P1 PS_DDR_DM2_502 DDR-DM2
502 AA2 PS_DDR_DM3_502 DDR-DM3
502 C2 PS_DDR_DQS_P0_502 DDR_DQS0 P
502 D2 PS_DDR_DQS_N0_502 DDR_DQS0 N
502 H2 PS_DDR_DQS_P1_502 DDR_DQS1 P
502 J2 PS_DDR_DQS_N1_502 DDR_DQS1 N
502 P2 PS_DDR_DQS_P2_502 DDR_DQS2 P
502 N2 PS_DDR_DQS_N2_502 DDR_DQS2 N
502 W2 PS_DDR_DQS_P3_502 DDR_DQS3 P
502 V2 PS_DDR_DQS_N3_502 DDR_DQS3 N
UART
TityraCore Z7 SoC SoDIMM supports UART pins connected to Bank 501 of PS and works at 1.8V voltage.
Bank Pin No: Signal Name Function
502 D11 PS_MIO48_501 UART_TX
502 C14 PS_MIO49_501 UART_RX
QSPI Flash
The TityraCore Z7 SoC SoDIMM has 128 Mb of Quad bit SPI flash memory. It is a serial NOR flash which operates at the voltage of 3.3 V. It is connected to QSPI controller of the PS and serves as the default primary boot device. Memory size of QSPI flash memory can be expanded to 8GB using eMMC flash.
Bank Pin No. Signal Name Function
500 A1
PS_MIO1_500 SPI_CS_N
500 A2
PS_MIO2_500 SPI_DQ[0]
500 F6 PS_MIO3_500 SPI_DQ[1]
500 E4 PS_MIO4_500 SPI_DQ[2]
500 A3 PS_MIO5_500 SPI_DQ[3]
500 A4 PS_MIO6_500 SPI_SCK
MicroSD Card
The TityrCore Z7 SoC SoDIMM have microSD card feature that can be incorporated in the carrier board. SD Card can be used to store non-volatile external memory and also can be used as a mean for secondary booting. It is directly connected to the SD0 controller of the PS MIO bank and operates at 1.8 V. The SD card can be accessed through the SD card connector in the carrier board.
Bank Pin No. Signal Name Function
501 E14 PS_MIO40_501 SD0_CLK
501 C8 PS_MIO41_501 SD0_CMD
501 D8 PS_MIO42_501 SD0_DAT0
501 B11 PS_MIO43_501 SD0_DAT1
501 E13 PS_MIO44_501 SD0_DAT2
501 B9 PS_MIO45_501 SD0_DAT3
eMMC Flash
TityraCore Z7 SoC SoDIMM supports 8 GB of eMMC flash memory for additional storage which is expandable up to 64 GB. It operates at a voltage level of 3.3 V and is connected to SD1 controller of the PS MIO bank . It has four data lines and function as a secondary boot device.
Bank Pin No. Signal Name Function
500 G7 PS_MIO10_500 eMMC_DAT0
500 B4 PS_MIO11_500 eMMC_CMD
500 C5 PS_MIO12_500 eMMC_CLK
500 A6 PS_MIO13_500 eMMC_DAT1
500 B6 PS_MIO14_500 eMMC_DAT2
500 E6 PS_MIO15_500 eMMC_DAT3
Ethernet
TityraCore Z7 SoC SoDIMM implements single-Chip 10/100/1000 Mbps Ethernet Transceiver, with 1.8 V IO operating voltage using Gigabit ethernet PHY “KSZ9031RNX”. It provides the Reduced Gigabit Media Independent Interface (RGMII) and is connected to the ENET0 interface of PS MIO bank in Zynq-7000 SOC. It operates in 1.8 V and also supports Link and Activity LED indication in carrier board. Ethernet functionality can be accessed through RJ45 Jack in the carrier board.
Bank Pin No. Signal Name Function
501 D6 PS_MIO16_501 ETH_TXCLK
501 E9 PS_MIO17_501 ETH_TXD0
501 A7 PS_MIO18_501 ETH_TXD1
501 E10 PS_MIO19_501 ETH_TXD2
501 A8 PS_MIO20_501 ETH_TXD3
501 F11 PS_MIO21_501 ETH_TXCTL
501 A14 PS_MIO22_501 ETH_RXCLK
501 E11 PS_MIO23_501 ETH_RXD0
501 B7 PS_MIO24_501 ETH_RXD1
501 F12 PS_MIO25_501 ETH_RXD2
501 A13 PS_MIO26_501 ETH_RXD3
501 D7 PS_MIO27_501 ETH_RXCTL
501 D10 PS_MIO52_501 ETH_MDC
501 C12 PS_MIO53_501 ETH_MDIO
USB 2.0 OTG
TityraCore Z7 SoC SoDIMM support high speed USB 2.0 On-The-Go (OTG) transceiver with 24 MHz operating frequency. It uses “USB3340” ULPI transceiver and supports both device and host modes. The ULPI (UTMI+ Low Pin Interface) protocol is utilized to establish a connection between MIO pins and the PHY component. It is connected to the OTG controller of PS MIO bank and works at 1.8V voltage.
The VBUS and USB ID pins play crucial roles in determining whether the OTG operates in Host mode, Device mode, or OTG mode.
Bank Pin No. Signal Name Function
501 A12 PS_MIO28_501 USB_D4
501 E8 PS_MIO29_501 USB_DIR
501 A11 PS_MIO30_501 USB_STP
501 F9 PS_MIO31_501 USB_NXT
501 C7 PS_MIO32_501 USB_D0
501 G13 PS_MIO33_501 USB_D1
501 B12 PS_MIO34_501 USB_D2
501 F14 PS_MIO35_501 USB_D3
501 A9 PS_MIO36_501 USB_CLK
501 B14 PS_MIO37_501 USB_D5
501 F13 PS_MIO38_501 USB_D6
501 C13 PS_MIO39_501 USB_D7
MAC EEPROM
TityraCore Z7 SoC SoDIMM features MAC ID EEPROM, which is a memory chip that stores the unique MAC address of a network interface. It is a non-volatile memory that interfaces with PS MIO Bank501 of Zynq-7000 AP SoC. It operates at a voltage of 1.8 V.
Bank Pin No Signal name Function
501 d12 PS_MIO46_501 MAC_SCL
501 b10 PS_MIO47_501 MAC_SDA
CAN
The TityraCore Z7 SoC SoDIMM facilitates CAN communication via the PS CAN controller and provides a versatile and effective means of establishing connections with diverse peripheral devices utilizing the CAN protocol. It has a operating voltage of 1.8 V.
Bank Pin No. Signal Name Function
501 D13 PS_MIO50_501 CAN_RX
501 C10 PS_MIO51_501 CAN_TX
Real Time Clock
TityraCore Z7 SoC SODIMM includes Real Time Clock (RTC), an integral part of electronic devices that operates independently of the device to accurately track real-world time. It is connected to PL Bank33 and has an operating voltage of 3.3 V. The carrier should include a coin cell battery to provide low power in the absence of an external power supply.
Bank Pin No Signal Name Function
33 W17 IO_L13P_T2_MRCC_33 RTSCL
33 W18 IO_L13N_T2_MRCC_33 RTSDA
RGB LED
The TityraCore SoC SoDIMM includes an RGB LED for user requirements. It is connected to PL Bank33 and has an operating voltage of 3.3 V.
Bank Pin No. Signal Name Function
33 V17 IO_L16N_T2_33 LED0
33 AA17 IO_L17P_T2_33 LED1
33 AB17 IO_L17N_T2_33 LED2
GPIO
Bank Pin No Signal
13 AA9 IO_L11P_T1_SRCC_13
13 AA8 IO_L11N_T1_SRCC_13
13 Y9 IO_L12P_T1_MRCC_13
13 Y8 IO_L12N_T1_MRCC_13
13 Y6 IO_L13P_T2_MRCC_13
13 Y5 IO_L13N_T2_MRCC_13
13 AA7 IO_L14P_T2_SRCC_13
13 AA6 IO_L14N_T2_SRCC_13
13 AB2 IO_L15P_T2_DQS_13
13 AB1 IO_L15N_T2_DQS_13
13 AB5 IO_L16P_T2_13
13 AB4 IO_L16N_T2_13
13 AB7 IO_L17P_T2_13
13 AB6 IO_L17N_T2_13
13 Y4 IO_L18P_T2_13
13 AA4 IO_L18N_T2_13
13 R6 IO_L19P_T3_13
13 T6 IO_L19N_T3_VREF_13
13 T4 IO_L20P_T3_13
13 U4 IO_L20N_T3_13
13 V5 IO_L21P_T3_DQS_13
13 V4 IO_L21N_T3_DQS_13
34 J15 IO_L1P_T0_34
34 K15 IO_L1N_T0_34
34 J16 IO_L2P_T0_34
34 J17 IO_L2N_T0_34
34 L17 IO_L4P_T0_34
34 M17 IO_L4N_T0_34
34 N17 IO_L5P_T0_34
34 N18 IO_L5N_T0_34
34 J20 IO_L9P_T1_DQS_34
34 K21 IO_L9N_T1_DQS_34
34 L21 IO_L10P_T1_34
34 L22 IO_L10N_T1_34
34 T16 IO_L21P_T3_DQS_34
34 T17 IO_L21N_T3_DQS_34
34 R19 IO_L22P_T3_34
34 T19 IO_L22N_T3_34
34 R18 IO_L23P_T3_34
34 T18 IO_L23N_T3_34
34 P16 IO_L24P_T3_34
34 R16 IO_L24N_T3_34
35 E16 IO_L1N_T0_AD0N_35
35 D16 IO_L2P_T0_AD8P_35
35 D17 IO_L2N_T0_AD8N_35
35 E15 IO_L3P_T0_DQS_AD1P_35
35 D15 IO_L3N_T0_DQS_AD1N_35
35 G15 IO_L4P_T0_35
35 G16 IO_L4N_T0_35
35 F18 IO_L5P_T0_AD9P_35
35 E18 IO_L5N_T0_AD9N_35
35 G17 IO_L6P_T0_35
35 F17 IO_L6P_T0_VREF_35
35 C15 IO_L7P_T1_AD2P_35
35 B15 IO_L7N_T1_AD2N_35
35 B16 IO_L8P_T1_AD10P_35
35 B17 IO_L8N_T1_AD10N_35
35 A16 IO_L9P_T1_DQS_AD3P_35
35 A17 IO_L9N_T1_DQS_AD3N_35
35 A18 IO_L10P_T1_AD11P_35
35 A19 IO_L10N_T1_AD11N_35
35 C17 IO_L11P_T1_SRCC_35
35 C18 IO_L11N_T1_SRCC_35
35 D18 IO_L12P_T1_MRCC_35
35 C19 IO_L12N_T1_MRCC_35
35 B19 IO_L13P_T2_MRCC_35
35 B20 IO_L13N_T2_MRCC_35
35 D20 IO_L14P_T2_AD4P_SRCC_35
35 C20 IO_L14N_T2_AD4N_SRCC_35
35 A21 IO_L15P_T2_DQS_AD12P_35
35 A22 IO_L15N_T2_DQS_AD12N_35
35 D22 IO_L16P_T2_35
35 C22 IO_L16N_T2_35
35 E21 IO_L17P_T2_AD5P_35
35 D21 IO_L17N_T2_AD5N_35
35 B21 IO_L18P_T2_AD13P_35
35 B22 IO_L18N_T2_AD13N_35
35 H19 IO_L19P_T3_35
35 H20 IO_L19N_T3_VREF_35
35 G19 IO_L20P_T3_AD6P_35
35 F19 IO_L20N_T3_AD6N_35
35 E19 IO_L21P_T3_DQS_AD14P_35
35 E20 IO_L21N_T3_DQS_AD14N_35
35 G20 IO_L22P_T3_AD7P_35
35 G21 IO_L22N_T3_AD7N_35
35 F21 IO_L23P_T3_35
35 F22 IO_L23N_T3_35
35 H22 IO_L24P_T3_AD15P_35
35 G22 IO_L24N_T3_AD15N_35
33 T21 IO_L1P_T0_33
33 U21 IO_L1N_T0_33
33 T22 IO_L2P_T0_33
33 U22 IO_L2N_T0_33
33 V22 IO_L3P_T0_DQS_33
33 W22 IO_L3N_T0_DQS_33
33 W20 IO_L4P_T0_33
33 W21 IO_L4N_T0_33
33 U20 IO_L5P_T0_33
33 V20 IO_L5N_T0_33
33 V18 IO_L6P_T0_33
33 V19 IO_L6N_T0_VREF_33
33 AA22 IO_L7P_T1_33
33 AB22 IO_L7N_T1_33
33 AA21 IO_L8P_T1_33
33 AB21 IO_L8N_T1_33
33 Y20 IO_L9P_T1_DQS_33
33 Y21 IO_L9N_T1_DQS_33
33 AB19 IO_L10P_T1_33
33 AB20 IO_L10N_T1_33
33 Y19 IO_L11P_T1_SRCC_33
33 AA19 IO_L11N_T1_SRCC_33
33 Y18 IO_L12P_T1_MRCC_33
33 AA18 IO_L12N_T1_MRCC_33
33 U17 IO_L16P_T2_33
33 V17 IO_L16N_T2_33
33 AA17 IO_L17P_T2_33
33 AB17 IO_L17N_T2_33
33 AA16 IO_L18P_T2_33
33 AB16 IO_L18N_T2_33
33 V14 IO_L19P_T3_33
33 V15 IO_L19N_T3_VREF_33
33 V13 IO_L20P_T3_33
33 W13 IO_L20NT3_33
33 W15 IO_L21P_T3_DQS_33
33 Y15 IO_L21N_T3_DQS_33
33 Y14 IO_L22P_T3_33
33 AA14 IO_L22N_T3_33
33 Y13 IO_L23P_T3_33
33 AA13 IO_L23N_T3_33
33 AB14 IO_L24P_T3_33
33 AB15 IO_L24N_T3_33
SODIMM Connector Pinout
Signal Name SODIMM Pin(Top) SODIMM Pin(Bottom) Signal Name
GND 1 2 GPHY_ATXRX_P
n_RST_IN 3 4 GPHY_ATXRX_N
GND 5 6 GPHY_BTXRX_P
MIPI_LANE0_P 7 8 GPHY_BTXRX_N
MIPI_LANE0_N 9 10 GND
MIPI_LANE1_P 11 12 GPHY_CTXRX_P
MIPI_LANE1_N 13 14 GPHY_CTXRX_N
MIPI_CLK_P 15 16 GPHY_DTXRX_P
MIPI_CLK_N 17 18 GPHY_DTXRX_N
CAM_PWUP 19 20 GND
CAM_CLK 21 22 GPHY_ACTIVITY_LED1
CAM_SCL 23 24 VCC3V3
CAM_SDA 25 26 GPHY_LINK_LED2
GND 27 28 SPI_DQ2
FPGA_TDI 29 30 SPI_DQ3
FPGA_TDO 31 32 VCC3V3
FPGA_TMS 33 34 FMC_PG_ALL
FPGA_TCK 35 36 VCC3V3
UART_TX 37 38 PROGRAM_B
UART_RX 39 40 GND
GND 41 42 CAN_TX
SD0_CLK 43 44 CAN_RX
SD0_CMD 45 46 VCC3V3
GND 47 48 PL_IO_L10_T1_AD11_35_P
SD0_DATA0 49 50 PL_IO_L10_T1_AD11_35_N
SD0_DATA1 51 52 PL_IO_L8_T1_AD10_35_P
SD0_DATA2 53 54 PL_IO_L8_T1_AD10_35_N
SD0_DATA3 55 56 PL_IO_L9_T1_DQS_AD3_35_P
FMC_PRESENT 57 58 PL_IO_L9_T1_DQS_AD3_35_N
NC 59 60 VCC3V3
PL_IO_L11_T1_SRCC_35_P 61 62 PL_IO_L7_T1_AD2_35_P
PL_IO_L11_T1_SRCC_35_N 63 64 PL_IO_L7_T1_AD2_35_N
GND 65 66 PL_IO_L1_T0_AD0_35_P
IO_L6_T0_13_P 67 68 PL_IO_L1_T0_AD0_35_N
IO_L6_T0_13_N 69 70 IO_L4_T0_13_P
IO_L1_T0_13_P 71 72 VCC3V3
IO_L1_T0_13_N 73 74 IO_L4_T0_13_N
IO_L2_T0_13_P 75 76 PL_IO_L6_T0_35_P
IO_L2_T0_13_N 77 78 PL_IO_L6_T0_35_N
GND 79 80 PL_IO_L5_T0_AD9_35_P
PL_IO_L17_T2_AD5_35_P 81 82 PL_IO_L5_T0_AD9_35_N
PL_IO_L17_T2_AD5_35_N 83 84 IO_L11_T1_SRCC_13_P
PL_IO_L24_T3_AD15_35_P 85 86 IO_L11_T1_SRCC_13_N
PL_IO_L24_T3_AD15_35_N 87 88 VCC3V3
IO_L12_T1_MRCC_13_P 89 90 PL_IO_L23_T3_35_P
IO_L12_T1_MRCC_13_N 91 92 PL_IO_L23_T3_35_N
IO_L5_T0_13_P 93 94 PL_IO_L16_T2_35_P
GND 95 96 PL_IO_L16_T2_35_N
IO_L5_T0_13_N 97 98 IO_L3_T0_DQS_13_P
PL_IO_L14_T2_AD4_SRCC_35_P 99 100 IO_L3_T0_DQS_13_N
PL_IO_L14_T2_AD4_SRCC_35_N 101 102 PL_IO_L18_T2_AD13_35_P
PL_IO_L15_T2_DQS_AD12_35_P 103 104 PL_IO_L18_T2_AD13_35_N
PL_IO_L15_T2_DQS_AD12_35_N 105 106 VCC3V3
IO_L7_T1_13_P 107 108 IO_L9_T1_DQS_13_P
IO_L7_T1_13_N 109 110 IO_L9_T1_DQS_13_N
IO_L8_T1_13_P 111 112 PL_IO_L2_T0_AD8_35_P
GND 113 114 PL_IO_L2_T0_AD8_35_N
IO_L8_T1_13_N 115 116 PL_IO_L13_T2_MRCC_35_P
PL_IO_L12_T1_MRCC_35_P 117 118 PL_IO_L13_T2_MRCC_35_N
PL_IO_L12_T1_MRCC_35_N 119 120 PL_IO_L4_T0_35_P
PL_IO_L3_T0_DQS_AD1_35_P 121 122 PL_IO_L4_T0_35_N
PL_IO_L3_T0_DQS_AD1_35_N 123 124 VCC3V3
PL_IO_L22_T3_AD7_35_P 125 126 PL_IO_L19_T3_35_P
PL_IO_L22_T3_AD7_35_N 127 128 PL_IO_L19_T3_35_N
PL_IO_L20_T3_AD6_35_P 129 130 PL_IO_L21_T3_DQS_AD14_35_P
GND 131 132 PL_IO_L21_T3_DQS_AD14_35_N
PL_IO_L20_T3_AD6_35_N 133 134 IO_L24_T3_33_P
IO_L23_T3_33_P 135 136 IO_L24_T3_33_N
IO_L23_T3_33_N 137 138 IO_L24_T3_34_P
IO_L22_T3_33_P 139 140 IO_L24_T3_34_N
IO_L22_T3_33_N 141 142 VCC3V3
IO_L4_T0_33_P 143 144 IO_L23_T3_34_P
IO_L4_T0_33_N 145 146 IO_L23_T3_34_N
IO_L3_T0_DQS_33_P 147 148 IO_L1_T0_33_P
IO_L3_T0_DQS_33_N 149 150 IO_L1_T0_33_N
GND 151 152 IO_L22_T3_34_P
IO_L2_T0_33_N 153 154 IO_L22_T3_34_N
IO_L2_T0_33_P 155 156 IO_L9_T1_DQS_34_P
IO_L21_T3_DQS_34_P 157 158 IO_L9_T1_DQS_34_N
IO_L21_T3_DQS_34_N 159 160 VCC3V3
IO_L19_T3_33_P 161 162 IO_L10_T1_34_P
IO_L19_T3_33_N 163 164 IO_L10_T1_34_N
IO_L16_T2_33_P 165 166 IO_L18_T2_33_P
IO_L16_T2_33_N 167 168 IO_L18_T2_33_N
GND 169 170 IO_L20_T3_33_P
IO_L17_T2_33_P 171 172 IO_L20_T3_33_N
IO_L17_T2_33_N 173 174 IO_L21_T3_DQS_33_P
IO_L12_T1_MRCC_33_P 175 176 IO_L21_T3_DQS_33_N
IO_L12_T1_MRCC_33_N 177 178 IO_L10_T1_33_P
IO_L11_T1_SRCC_33_P 179 180 VCC3V3
IO_L11_T1_SRCC_33_N 181 182 IO_L10_T1_33_N
IO_L7_T1_33_P 183 184 IO_L8_T1_33_P
GND 185 186 GND
IO_L7_T1_33_N 187 188 IO_L8_T1_33_N
IO_L9_T1_DQS_33_P 189 190 USB_ID
IO_L9_T1_DQS_33_N 191 192 USB_5V
IO_L5_T0_33_P 193 194 OTG_D_P
IO_L5_T0_33_N 195 196 OTG_D_N
IO_L6_T0_33_P 197 198 GND
IO_L6_T0_33_N 199 200 VCC5V0
Getting Started With Development on TityraCore
Workflow for the Zynq series is slightly different than Series-7 FPGAs. There is a tutorial on quickly getting up and running with TityraCore to accelerate the pace of development.
Link: https://docs.numato.com/kb/getting-started-zynq-on-styx-using-vivado-design-suite/
Powering Up TityraCore
TityraCore is factory configured to be powered only from the carrier so make sure that you a carrier that can power the board properly.
Generating Bit Stream for TityraCore
The bitstream can be generated for TityraCore in Vivado by following the steps below:
Step 1: It is recommended to generate .bin file along with .bit file. Right-click on “Generate Bitstream” under the “Program and Debug” section of the Flow Navigator window and click “Bitstream Settings”.
Step 2: Select “-bin_file” option in the dialog window and click “Apply” and then “OK”.
Step 3: Finally click “Generate Bitstream”.
Programming TityraCore Module Using JTAG
TityraCore Z7 SoC SoDIMM facilitates easy reprogramming of SRAM and onboard SPI flash through JTAG programmer like “Xilinx Platform cable USB”. Following steps illustrate how to program FPGA on TityraCore using JTAG.
Step 1: By using JTAG cable, connect Xilinx platform cable USB to the carrier of TityraCore and power it up.
Step 2: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.
Step 3: If the device is detected successfully, then select “Program Device” after right clicking on the target device “xc7z020_1 (1)” as shown below.
Step 4: In the dialog window which opens up, Vivado automatically chooses the correct bitstream file if the design was synthesized, implemented and bitstream generated successfully. If needed, browse to the bitstream which needs to be programmed to FPGA. Finally, click “Program”.
Programming QSPI Flash
Programming the QSPI Flash for the Zynq series is slightly different than Series-7 FPGAs. There is a tutorial on how to boot Styx from QSPI (as well as SD Card). Follow the same steps for TityraCore Z7 SoC module also.
Link: Styx: Boot from SD card and QSPI flash
Technical Specifications
Parameter * Value Unit
Basic Specifications
Number of GPIOs 126
On-board oscillator frequency 33.33 MHz
On-board oscillator frequency (ASEM1-50.000MHZ-LC-T) 50 MHz
DDR3L Capacity 2 GB
Quad SPI Flash Memory (MT25QL01GBBB8E12) 1 GB
Power supply voltage (External) 5, 3.3 V
Internal Processor Core Voltage 1.0 V
Auxiliary supply voltage relative to GND 1.8 V
Output drivers supply voltage relative to GND -0.5 to 3.6 V
PS MIO I/O supply voltage (VCCO_MIO) 1.8, 3.3 V
PS MIO I/O input voltage 1.8, 3.3 V
PS DDR I/O input voltage 1.35 or 1.5 V
Maximum Processor Frequency 667 MHz
* All parameters considered nominal. Numato Systems Pvt Ltd reserves the right to modify products without notice.
Mechanical Dimensions
Vivado XDC Constraints
Help Guide Powered by Documentor
TityraCore Z7 SoC SoDIMM
0 views September 24, 2024 milna-ms 0