TityraCore SODIMM

TityraCore Z7 SoC SoDIMM

0 views September 24, 2024 milna-ms 0

Introduction

TityraCore Z7 SoC SoDIMM incorporates the AMD Zynq XC7Z020 chip, seamlessly integrating programmable logic with a dual-core ARM Cortex-A9 processor. This integration provides a potent blend of hardware and software processing capabilities, all within a single chip. Zynq series features a hard System on Chip (SoC) with an ARM core. The range of peripherals offered includes an extensive array of functionalities, such as UARTs, Ethernet controllers, USB ports, timers, interrupt controllers, and various other features. It has a seamless integration of the Processing System(PS) with the Programmable Logic (PL) in which the interaction between them is enabled by a high-bandwidth interface, ensuring communication and efficient data transfer between them. TityraCore Z7 SoC SoDIMM is specifically designed for the development and integration of FPGA-based accelerated features into other larger designs. It opens up a vast realm of possibilities for implementing innovative solutions across various applications.

Yes No Suggest edit

Board features

  • Device: XC7Z020 in CLG484 package, Speed Grade: -1
  • SDRAM: 2 GB DDR3L (MT41K256M16TW-107 IT:P TR or equivalent)
  • Flash memory: 128 Mb Quad bit SPI flash memory (N25Q128A13EF840E)
  • 33 MHz CMOS oscillator
  • 50 MHz CMOS oscillator
  • Gigabit Ethernet, Real Time Clock, CAN BUS, MAC ID
  • MIPI interfacing
  • High-Speed USB 2.0 OTG interface.
  • JTAG and USB programming
  • Micro SD card for memory expansion
  • 8 Gb eMMC
Yes No Suggest edit

Application

  • Product Prototype Development
  • Accelerated computing integration
  • Custom Embedded platform
  • Signal Processing
  • Communication devices development
  • Educational tool for Schools and Universities
Yes No Suggest edit

Components/Tools required

Along with the module, you may need the items in the list below for easy and fast installation.

  1. Carrier board
  2. Micro-B cable.
  3. USB-C cable
  4. A Xilinx Platform Cable USB II compatible JTAG programmer
  5. DC Power supply
Yes No Suggest edit

Connection Diagram

Reference clock

BankPin No.Signal NameFunction
500F7PS_CLK_50033.33 MHz CLK
34W17
IO_L13P_T2_MRCC_33
50 MHz CLK
Yes No Suggest edit

Reset

BankPin No.Signal nameFunction
501C9PS_SRST_B_501n RST IN
500B5PS_POR_B_500Program B
Yes No Suggest edit

DDR3L SDRAM

TityraCore Z7 SoC SoDIMM includes DDR3L memory technology which is the third generation of DDR memory technology designed to operate at lower voltage levels (1.35 V) compared to standard DDR3 modules. TityraCore Z7 SoC SoDIMM uses micron MT41K256M16TW-107 IT:P TR memory which has a capacity of  2 GB of RAM.

BankPin No.Signal NameFunction
502D1PS_DDR_DQ0_502DDR-DQ0
502C3PS_DDR_DQ1_502DDR-DQ1
502B2PS_DDR_DQ2_502DDR-DQ2
502D3PS_DDR_DQ3_502DDR-DQ3
502E3PS_DDR_DQ4_502DDR-DQ4
502E1PS_DDR_DQ5_502DDR-DQ5
502F2PS_DDR_DQ6_502DDR-DQ6
502F1PS_DDR_DQ7_502DDR-DQ7
502G2PS_DDR_DQ8_502DDR-DQ8
502G1PS_DDR_DQ9_502DDR-DQ9
502L1PS_DDR_DQ10_502DDR-DQ10
502L2PS_DDR_DQ11_502DDR-DQ11
502L3PS_DDR_DQ12_502DDR-DQ12
502K1PS_DDR_DQ13_502DDR-DQ13
502J1PS_DDR_DQ14_502DDR-DQ14
502K3PS_DDR_DQ15_502DDR-DQ15
502M1PS_DDR_DQ16_502DDR-DQ16
502T3PS_DDR_DQ17_502DDR-DQ17
502N3PS_DDR_DQ18_502DDR-DQ18
502T1PS_DDR_DQ19_502DDR-DQ19
502R3PS_DDR_DQ20_502DDR-D20
502T2PS_DDR_DQ21_502DDR-DQ21
502M2PS_DDR_DQ22_502DDR-DQ22
502R1PS_DDR_DQ23_502DDR-DQ23
502AA3PS_DDR_DQ24_502DDR-DQ24
502U1PS_DDR_DQ25_502DDR-DQ25
502AA1PS_DDR_DQ26_502DDR-DQ26
502U2PS_DDR_DQ27_502DDR-DQ27
502W1PS_DDR_DQ28_502DDR-DQ28
502Y3PS_DDR_DQ29_502DDR-DQ29
502W3PS_DDR_DQ30_502DDR-DQ30
502Y1PS_DDR_DQ31_502DDR-DQ31
502M4PS_DDR_A0_502DDR0-A0
502M5PS_DDR_A1_502DDR0-A1
502K4PS_DDR_A2_502DDR0-A2
502L4PS_DDR_A3_502DDR0-A3
502K6PS_DDR_A4_502DDR0-A4
502K5PS_DDR_A5_502DDR0-A5
502J7PS_DDR_A6_502DDR0-A6
502J6PS_DDR_A7_502DDR0-A7
502J5PS_DDR_A8_502DDR0-A8
502H5PS_DDR_A9_502DDR0-A9
502J3PS_DDR_A10_502DDR0-A10
502G5PS_DDR_A11_502DDR0-A11
502H4PS_DDR_A12_502DDR0-A12
502F4PS_DDR_A13_502DDR0-A13
502G4PS_DDR_A14_502DDR0-A14
502L7PS_DDR_BA0_502DDR-BA0
502L6PS_DDR_BA1_502DDR-BA1
502M6PS_DDR_BA2_502DDR-BA2
502P6PS_DDR_CS_B_502DDR0-CS#
502R5PS_DDR_RAS_B_502DDR0-RAS
502P3PS_DDR_CAS_B_502DDR0-CAS
502R4PS_DDR_WE_B_502DDR0-WE
502N5PS_DDR_CKN_502DDR0-CK N
502N4PS_DDR_CKP_502DDR0-CK P
502V3PS_DDR_CKE_502DDR0-CKE
502F3PS_DDR_DRST_B_502DDR0-RESET
502P5PS_DDR_ODT_502DDR0-ODT
502B1PS_DDR_DM0_502DDR-DM0
502H3PS_DDR_DM1_502DDR-DM1
502P1PS_DDR_DM2_502DDR-DM2
502AA2PS_DDR_DM3_502DDR-DM3
502C2PS_DDR_DQS_P0_502DDR_DQS0 P
502D2PS_DDR_DQS_N0_502DDR_DQS0 N
502H2PS_DDR_DQS_P1_502DDR_DQS1 P
502J2PS_DDR_DQS_N1_502DDR_DQS1 N
502N2PS_DDR_DQS_P2_502DDR_DQS2 P
502P2PS_DDR_DQS_N2_502DDR_DQS2 N
502V2PS_DDR_DQS_P3_502DDR_DQS3 P
502W2PS_DDR_DQS_N3_502DDR_DQS3 N
Yes No Suggest edit

UART

TityraCore Z7 SoC SoDIMM supports UART pins connected to Bank 501 of PS and works at 1.8V voltage.

BankPin No:Signal NameFunction
502D11PS_MIO48_501UART_TX
502C14PS_MIO49_501UART_RX
Yes No Suggest edit

QSPI Flash

The TityraCore Z7 SoC SoDIMM has 128 Mb of Quad bit SPI flash memory. It is a serial NOR flash which operates at the voltage of 3.3 V. It is connected to QSPI controller of the PS and serves as the default primary boot device. Memory size of QSPI flash memory can be expanded to 8GB using eMMC flash.

BankPin No.Signal NameFunction
500A1
PS_MIO1_500SPI_CS_N
500A2
PS_MIO2_500SPI_DQ[0]
500F6PS_MIO3_500SPI_DQ[1]
500E4PS_MIO4_500SPI_DQ[2]
500A3PS_MIO5_500SPI_DQ[3]
500A4PS_MIO6_500SPI_SCK
Yes No Suggest edit

MicroSD Card

The TityrCore Z7 SoC SoDIMM have microSD card feature that can be incorporated in the carrier board. SD Card can be used to store non-volatile external memory and also can be used as a mean for secondary booting. It is directly connected to the SD0 controller of the PS MIO bank  and operates at 1.8 V. The SD card can be accessed through the SD card connector in the carrier board.

BankPin No.Signal NameFunction
501E14PS_MIO40_501SD0_CLK
501C8PS_MIO41_501SD0_CMD
501D8PS_MIO42_501SD0_DAT0
501B11PS_MIO43_501SD0_DAT1
501E13PS_MIO44_501SD0_DAT2
501B9PS_MIO45_501SD0_DAT3
Yes No Suggest edit

eMMC Flash

TityraCore Z7 SoC SoDIMM supports 8 GB of eMMC flash memory for additional storage which is expandable up to 64 GB. It operates at a voltage level of 3.3 V and is connected to SD1 controller of the PS MIO bank . It has four data lines and function as a secondary boot device.

BankPin No.Signal NameFunction
500G7PS_MIO10_500eMMC_DAT0
500B4PS_MIO11_500eMMC_CMD
500C5PS_MIO12_500eMMC_CLK
500A6PS_MIO13_500eMMC_DAT1
500B6PS_MIO14_500eMMC_DAT2
500E6PS_MIO15_500eMMC_DAT3
Yes No Suggest edit

Ethernet

TityraCore Z7 SoC SoDIMM implements single-Chip 10/100/1000 Mbps Ethernet Transceiver, with 1.8 V IO operating voltage using Gigabit ethernet PHY “KSZ9031RNX”. It provides the Reduced Gigabit Media Independent Interface (RGMII) and is connected to the ENET0 interface of PS MIO bank in Zynq-7000 SOC. It operates in 1.8 V and also supports Link and Activity LED indication in carrier board. Ethernet functionality can be accessed through RJ45 Jack in the carrier board.

BankPin No.Signal NameFunction
501D6PS_MIO16_501ETH_TXCLK
501E9PS_MIO17_501ETH_TXD0
501A7PS_MIO18_501ETH_TXD1
501E10PS_MIO19_501ETH_TXD2
501A8PS_MIO20_501ETH_TXD3
501F11PS_MIO21_501ETH_TXCTL
501A14PS_MIO22_501ETH_RXCLK
501E11PS_MIO23_501ETH_RXD0
501B7PS_MIO24_501ETH_RXD1
501F12PS_MIO25_501ETH_RXD2
501A13PS_MIO26_501ETH_RXD3
501D7PS_MIO27_501ETH_RXCTL
501D10PS_MIO52_501ETH_MDC
501C12PS_MIO53_501ETH_MDIO
Yes No Suggest edit

USB 2.0 OTG

TityraCore Z7 SoC SoDIMM support high speed USB 2.0 On-The-Go (OTG) transceiver with 24 MHz operating frequency. It uses “USB3340” ULPI transceiver and supports both device and host modes. The ULPI (UTMI+ Low Pin Interface) protocol is utilized to establish a connection between MIO pins and the PHY component. It is connected to the OTG controller of PS MIO bank and works at 1.8V voltage.

The VBUS and USB ID pins play crucial roles in determining whether the OTG operates in Host mode, Device mode, or OTG mode.

BankPin No.Signal NameFunction
501A12PS_MIO28_501USB_D4
501E8PS_MIO29_501USB_DIR
501A11PS_MIO30_501USB_STP
501F9PS_MIO31_501USB_NXT
501C7PS_MIO32_501USB_D0
501G13PS_MIO33_501USB_D1
501B12PS_MIO34_501USB_D2
501F14PS_MIO35_501USB_D3
501A9PS_MIO36_501USB_CLK
501B14PS_MIO37_501USB_D5
501F13PS_MIO38_501USB_D6
501C13PS_MIO39_501USB_D7
Yes No Suggest edit

MAC EEPROM

TityraCore Z7 SoC SoDIMM features MAC ID EEPROM, which is a memory chip that stores the unique MAC address of a network interface. It is a non-volatile memory that interfaces with PS MIO Bank501 of Zynq-7000 AP SoC. It operates at a voltage of 1.8 V.

BankPin NoSignal nameFunction
501D12PS_MIO46_501MAC_SCL
501B10PS_MIO47_501MAC_SDA
Yes No Suggest edit

CAN

The TityraCore Z7 SoC SoDIMM facilitates CAN communication via the PS CAN controller and provides a versatile and effective means of establishing connections with diverse peripheral devices utilizing the CAN protocol. It has a operating voltage of 1.8 V.

BankPin No.Signal NameFunction
501D13PS_MIO50_501CAN_RX
501C10PS_MIO51_501CAN_TX
Yes No Suggest edit

Real Time Clock

TityraCore Z7 SoC SODIMM includes Real Time Clock (RTC), an integral part of electronic devices that operates independently of the device to accurately track real-world time. It is connected to PL Bank33 and has an operating voltage of 3.3 V. The carrier should include a coin cell battery to provide low power in the absence of an external power supply.

BankPin NoSignal NameFunction
33W18IO_L13N_T2_MRCC_33RTSCL
33W16IO_L14P_T2_MRCC_33RTSDA
Yes No Suggest edit

RGB LED

The TityraCore SoC SoDIMM includes an RGB LED for user requirements. It is connected to PL Bank33 and has an operating voltage of 3.3 V.

BankPin No.Signal NameFunction
33Y16IO_L14N_T2_SRCC_33LED0
33U15IO_L15P_T2_DQS_33LED1
33U16IO_L15N_T2_DQS_33LED2
Yes No Suggest edit

GPIO

BankPin NoSignal
13AA9IO_L11P_T1_SRCC_13
13AA8IO_L11N_T1_SRCC_13
13Y9IO_L12P_T1_MRCC_13
13Y8IO_L12N_T1_MRCC_13
13Y6IO_L13P_T2_MRCC_13
13Y5IO_L13N_T2_MRCC_13
13AA7IO_L14P_T2_SRCC_13
13AA6IO_L14N_T2_SRCC_13
13AB2IO_L15P_T2_DQS_13
13AB1IO_L15N_T2_DQS_13
13AB5IO_L16P_T2_13
13AB4IO_L16N_T2_13
13AB7IO_L17P_T2_13
13AB6IO_L17N_T2_13
13Y4IO_L18P_T2_13
13AA4IO_L18N_T2_13
13R6IO_L19P_T3_13
13T6IO_L19N_T3_VREF_13
13T4IO_L20P_T3_13
13U4IO_L20N_T3_13
13V5IO_L21P_T3_DQS_13
13V4IO_L21N_T3_DQS_13
34J15IO_L1P_T0_34
34K15IO_L1N_T0_34
34J16IO_L2P_T0_34
34J17IO_L2N_T0_34
34L17IO_L4P_T0_34
34M17IO_L4N_T0_34
34N17IO_L5P_T0_34
34N18IO_L5N_T0_34
34J20IO_L9P_T1_DQS_34
34K21IO_L9N_T1_DQS_34
34L21IO_L10P_T1_34
34L22IO_L10N_T1_34
34T16IO_L21P_T3_DQS_34
34T17IO_L21N_T3_DQS_34
34R19IO_L22P_T3_34
34T19IO_L22N_T3_34
34R18IO_L23P_T3_34
34T18IO_L23N_T3_34
34P16IO_L24P_T3_34
34R16IO_L24N_T3_34
35E16IO_L1N_T0_AD0N_35
35D16IO_L2P_T0_AD8P_35
35D17IO_L2N_T0_AD8N_35
35E15IO_L3P_T0_DQS_AD1P_35
35D15IO_L3N_T0_DQS_AD1N_35
35G15IO_L4P_T0_35
35G16IO_L4N_T0_35
35F18IO_L5P_T0_AD9P_35
35E18IO_L5N_T0_AD9N_35
35G17IO_L6P_T0_35
35F17IO_L6P_T0_VREF_35
35C15IO_L7P_T1_AD2P_35
35B15IO_L7N_T1_AD2N_35
35B16IO_L8P_T1_AD10P_35
35B17IO_L8N_T1_AD10N_35
35A16IO_L9P_T1_DQS_AD3P_35
35A17IO_L9N_T1_DQS_AD3N_35
35A18IO_L10P_T1_AD11P_35
35A19IO_L10N_T1_AD11N_35
35C17IO_L11P_T1_SRCC_35
35C18IO_L11N_T1_SRCC_35
35D18IO_L12P_T1_MRCC_35
35C19IO_L12N_T1_MRCC_35
35B19IO_L13P_T2_MRCC_35
35B20IO_L13N_T2_MRCC_35
35D20IO_L14P_T2_AD4P_SRCC_35
35C20IO_L14N_T2_AD4N_SRCC_35
35A21IO_L15P_T2_DQS_AD12P_35
35A22IO_L15N_T2_DQS_AD12N_35
35D22IO_L16P_T2_35
35C22IO_L16N_T2_35
35E21IO_L17P_T2_AD5P_35
35D21IO_L17N_T2_AD5N_35
35B21IO_L18P_T2_AD13P_35
35B22IO_L18N_T2_AD13N_35
35H19IO_L19P_T3_35
35H20IO_L19N_T3_VREF_35
35G19IO_L20P_T3_AD6P_35
35F19IO_L20N_T3_AD6N_35
35E19IO_L21P_T3_DQS_AD14P_35
35E20IO_L21N_T3_DQS_AD14N_35
35G20IO_L22P_T3_AD7P_35
35G21IO_L22N_T3_AD7N_35
35F21IO_L23P_T3_35
35F22IO_L23N_T3_35
35H22IO_L24P_T3_AD15P_35
35G22IO_L24N_T3_AD15N_35
33T21IO_L1P_T0_33
33U21IO_L1N_T0_33
33T22IO_L2P_T0_33
33U22IO_L2N_T0_33
33V22IO_L3P_T0_DQS_33
33W22IO_L3N_T0_DQS_33
33W20IO_L4P_T0_33
33W21IO_L4N_T0_33
33U20IO_L5P_T0_33
33V20IO_L5N_T0_33
33V18IO_L6P_T0_33
33V19IO_L6N_T0_VREF_33
33AA22IO_L7P_T1_33
33AB22IO_L7N_T1_33
33AA21IO_L8P_T1_33
33AB21IO_L8N_T1_33
33Y20IO_L9P_T1_DQS_33
33Y21IO_L9N_T1_DQS_33
33AB19IO_L10P_T1_33
33AB20IO_L10N_T1_33
33Y19IO_L11P_T1_SRCC_33
33AA19IO_L11N_T1_SRCC_33
33Y18IO_L12P_T1_MRCC_33
33AA18IO_L12N_T1_MRCC_33
33U17IO_L16P_T2_33
33V17IO_L16N_T2_33
33AA17IO_L17P_T2_33
33AB17IO_L17N_T2_33
33AA16IO_L18P_T2_33
33AB16IO_L18N_T2_33
33V14IO_L19P_T3_33
33V15IO_L19N_T3_VREF_33
33V13IO_L20P_T3_33
33W13IO_L20NT3_33
33W15IO_L21P_T3_DQS_33
33Y15IO_L21N_T3_DQS_33
33Y14IO_L22P_T3_33
33AA14IO_L22N_T3_33
33Y13IO_L23P_T3_33
33AA13IO_L23N_T3_33
33AB14IO_L24P_T3_33
33AB15IO_L24N_T3_33
Yes No Suggest edit

SODIMM Connector Pinout

Signal NameSODIMM Pin(Top)SODIMM Pin(Bottom)Signal Name
GND12GPHY_ATXRX_P
n_RST_IN34GPHY_ATXRX_N
GND56GPHY_BTXRX_P
MIPI_LANE0_P78GPHY_BTXRX_N
MIPI_LANE0_N910GND
MIPI_LANE1_P1112GPHY_CTXRX_P
MIPI_LANE1_N1314GPHY_CTXRX_N
MIPI_CLK_P1516GPHY_DTXRX_P
MIPI_CLK_N1718GPHY_DTXRX_N
CAM_PWUP1920GND
CAM_CLK2122GPHY_ACTIVITY_LED1
CAM_SCL2324VCC3V3
CAM_SDA2526GPHY_LINK_LED2
GND2728SPI_DQ2
FPGA_TDI2930SPI_DQ3
FPGA_TDO3132VCC3V3
FPGA_TMS3334FMC_PG_ALL
FPGA_TCK3536VCC3V3
UART_TX3738PROGRAM_B
UART_RX3940GND
GND4142CAN_TX
SD0_CLK4344CAN_RX
SD0_CMD4546VCC3V3
GND4748PL_IO_L10_T1_AD11_35_P
SD0_DATA04950PL_IO_L10_T1_AD11_35_N
SD0_DATA15152PL_IO_L8_T1_AD10_35_P
SD0_DATA25354PL_IO_L8_T1_AD10_35_N
SD0_DATA35556PL_IO_L9_T1_DQS_AD3_35_P
FMC_PRESENT5758PL_IO_L9_T1_DQS_AD3_35_N
NC5960VCC3V3
PL_IO_L11_T1_SRCC_35_P6162PL_IO_L7_T1_AD2_35_P
PL_IO_L11_T1_SRCC_35_N6364PL_IO_L7_T1_AD2_35_N
GND6566PL_IO_L1_T0_AD0_35_P
IO_L6_T0_13_P6768PL_IO_L1_T0_AD0_35_N
IO_L6_T0_13_N6970IO_L4_T0_13_P
IO_L1_T0_13_P7172VCC3V3
IO_L1_T0_13_N7374IO_L4_T0_13_N
IO_L2_T0_13_P7576PL_IO_L6_T0_35_P
IO_L2_T0_13_N7778PL_IO_L6_T0_35_N
GND7980PL_IO_L5_T0_AD9_35_P
PL_IO_L17_T2_AD5_35_P8182PL_IO_L5_T0_AD9_35_N
PL_IO_L17_T2_AD5_35_N8384IO_L11_T1_SRCC_13_P
PL_IO_L24_T3_AD15_35_P8586IO_L11_T1_SRCC_13_N
PL_IO_L24_T3_AD15_35_N8788VCC3V3
IO_L12_T1_MRCC_13_P8990PL_IO_L23_T3_35_P
IO_L12_T1_MRCC_13_N9192PL_IO_L23_T3_35_N
IO_L5_T0_13_P9394PL_IO_L16_T2_35_P
GND9596PL_IO_L16_T2_35_N
IO_L5_T0_13_N9798IO_L3_T0_DQS_13_P
PL_IO_L14_T2_AD4_SRCC_35_P99100IO_L3_T0_DQS_13_N
PL_IO_L14_T2_AD4_SRCC_35_N101102PL_IO_L18_T2_AD13_35_P
PL_IO_L15_T2_DQS_AD12_35_P103104PL_IO_L18_T2_AD13_35_N
PL_IO_L15_T2_DQS_AD12_35_N105106VCC3V3
IO_L7_T1_13_P107108IO_L9_T1_DQS_13_P
IO_L7_T1_13_N109110IO_L9_T1_DQS_13_N
IO_L8_T1_13_P111112PL_IO_L2_T0_AD8_35_P
GND113114PL_IO_L2_T0_AD8_35_N
IO_L8_T1_13_N115116PL_IO_L13_T2_MRCC_35_P
PL_IO_L12_T1_MRCC_35_P117118PL_IO_L13_T2_MRCC_35_N
PL_IO_L12_T1_MRCC_35_N119120PL_IO_L4_T0_35_P
PL_IO_L3_T0_DQS_AD1_35_P121122PL_IO_L4_T0_35_N
PL_IO_L3_T0_DQS_AD1_35_N123124VCC3V3
PL_IO_L22_T3_AD7_35_P125126PL_IO_L19_T3_35_P
PL_IO_L22_T3_AD7_35_N127128PL_IO_L19_T3_35_N
PL_IO_L20_T3_AD6_35_P129130PL_IO_L21_T3_DQS_AD14_35_P
GND131132PL_IO_L21_T3_DQS_AD14_35_N
PL_IO_L20_T3_AD6_35_N133134IO_L24_T3_33_P
IO_L23_T3_33_P135136IO_L24_T3_33_N
IO_L23_T3_33_N137138IO_L24_T3_34_P
IO_L22_T3_33_P139140IO_L24_T3_34_N
IO_L22_T3_33_N141142VCC3V3
IO_L4_T0_33_P143144IO_L23_T3_34_P
IO_L4_T0_33_N145146IO_L23_T3_34_N
IO_L3_T0_DQS_33_P147148IO_L1_T0_33_P
IO_L3_T0_DQS_33_N149150IO_L1_T0_33_N
GND151152IO_L22_T3_34_P
IO_L2_T0_33_N153154IO_L22_T3_34_N
IO_L2_T0_33_P155156IO_L9_T1_DQS_34_P
IO_L21_T3_DQS_34_P157158IO_L9_T1_DQS_34_N
IO_L21_T3_DQS_34_N159160VCC3V3
IO_L19_T3_33_P161162IO_L10_T1_34_P
IO_L19_T3_33_N163164IO_L10_T1_34_N
IO_L16_T2_33_P165166IO_L18_T2_33_P
IO_L16_T2_33_N167168IO_L18_T2_33_N
GND169170IO_L20_T3_33_P
IO_L17_T2_33_P171172IO_L20_T3_33_N
IO_L17_T2_33_N173174IO_L21_T3_DQS_33_P
IO_L12_T1_MRCC_33_P175176IO_L21_T3_DQS_33_N
IO_L12_T1_MRCC_33_N177178IO_L10_T1_33_P
IO_L11_T1_SRCC_33_P179180VCC3V3
IO_L11_T1_SRCC_33_N181182IO_L10_T1_33_N
IO_L7_T1_33_P183184IO_L8_T1_33_P
GND185186GND
IO_L7_T1_33_N187188IO_L8_T1_33_N
IO_L9_T1_DQS_33_P189190USB_ID
IO_L9_T1_DQS_33_N191192USB_5V
IO_L5_T0_33_P193194OTG_D_P
IO_L5_T0_33_N195196OTG_D_N
IO_L6_T0_33_P197198GND
IO_L6_T0_33_N199200VCC5V0
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Getting Started With Development on TityraCore

Workflow for the Zynq series is slightly different than Series-7 FPGAs. There is a tutorial on quickly getting up and running with TityraCore to accelerate the pace of development.

Link: https://docs.numato.com/kb/getting-started-zynq-on-styx-using-vivado-design-suite/

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Powering Up TityraCore

TityraCore is factory configured to be powered only from the carrier so make sure that you have a carrier that can power the board properly.

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Generating Bit Stream for TityraCore

The bitstream can be generated for TityraCore in Vivado by following the steps below:

Step 1:  It is recommended to generate .bin file along with .bit file. Right-click on “Generate Bitstream” under the “Program and Debug” section of the Flow Navigator window and click “Bitstream Settings”.

Step 2: Select “-bin_file” option in the dialog window and click “Apply” and then “OK”.

Step 3: Finally click “Generate Bitstream”.

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Programming TityraCore Module Using JTAG

TityraCore Z7 SoC SoDIMM facilitates easy reprogramming of SRAM and onboard SPI flash through JTAG programmer like “Xilinx Platform cable USB”. Following steps illustrate how to program FPGA on TityraCore using JTAG.

Step 1: By using JTAG cable, connect Xilinx platform cable USB to the carrier of TityraCore and power it up.

Step 2: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 3: If the device is detected successfully, then select “Program Device” after right clicking on the target device “xc7z020_1 (1)” as shown below.

Step 4: In the dialog window which opens up, Vivado automatically chooses the correct bitstream file if the design was synthesized, implemented and bitstream generated successfully. If needed, browse to the bitstream which needs to be programmed to FPGA. Finally, click “Program”.

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Programming QSPI Flash

Programming the QSPI Flash for the Zynq series is slightly different than Series-7 FPGAs. There is a tutorial on how to  boot Styx from QSPI (as well as SD Card). Follow the same steps for TityraCore Z7 SoC module also.
Link: Styx: Boot from SD card and QSPI flash

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Technical Specifications

Parameter *ValueUnit
Basic Specifications
Number of GPIOs126
On-board oscillator frequency33.33MHz
On-board oscillator frequency (ASEM1-50.000MHZ-LC-T)50MHz
DDR3L Capacity2GB
Quad SPI Flash Memory (MT25QL01GBBB8E12)1GB
Power supply voltage (External)5, 3.3V
Internal Processor Core Voltage1.0V
Auxiliary supply voltage relative to GND1.8V
Output drivers supply voltage relative to GND-0.5 to 3.6V
PS MIO I/O supply voltage (VCCO_MIO)1.8, 3.3V
PS MIO I/O input voltage1.8, 3.3V
PS DDR I/O input voltage1.35 or 1.5 V
Maximum Processor Frequency667MHz

* All parameters considered nominal. Numato Systems Pvt Ltd reserves the right to modify products without notice.

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Mechanical Dimensions

Vivado XDC Constraints

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