Intel MAX 10 FPGA Boards

Telesto MAX 10 FPGA Module

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Introduction

Telesto is an easy to use FPGA Module featuring Intel (formerly Altera) MAX 10 FPGA. The MAX 10 FPGAs come with dual embedded NOR Flash, with almost instant-on functionality hence eliminating the need for external configuration memory. The dual configuration flash on MAX 10 allows users to store and dynamically switch between two bitstreams on a single chip. They also feature integrated Analog-to-Digital Converters (ADCs). Telesto is pin compatible with Saturn Spartan 6 FPGA ModuleNeso Artix 7 FPGA Module , Skoll Kintex 7 FPGA Module as well as Styx Zynq FPGA Module and offers a seamless upgrade path. The high speed USB 2.0 provides fast and easy configuration download to the built-in flash via JTAG using OpenOCD. No programmer or special downloader cable is needed to download the bitstream to the board. Telesto provides users with flexibility in adding their own peripherals through IOs available on its headers.

Board Features

  • Pin compatible with Saturn Spartan 6 FPGA ModuleNeso Artix 7 FPGA Module, Skoll Kintex 7 FPGA Module and Styx Zynq FPGA Module and offers a seamless upgrade path
  • Device: MAX 10 FPGA (10M16DA or 10M50DA, F484 package and Speed Grade: -C8)
  • DDR3: 2Gb DDR3 (MT41J128M16HA-125:K or equivalant)
  • Internal Flash Memory
  • 100MHz LVDS oscillator
  • High Speed USB 2.0 interface. FT2232H Channel A can be used for custom applications. Channel B is connected to MAX 10 JTAG.
  • Onboard voltage regulators for single power rail operation
  • FPGA configuration via external JTAG and USB
  • Maximum IOs for user-defined purposes
    • FPGA – 150 IOs
    • Analog Inputs – 8 IOs

Applications

  • Product Prototype Development
  • Accelerated computing integration
  • Development and testing of custom embedded processors
  • Signal Processing
  • Communication devices development
  • Educational tool for Schools and Universities
  • System monitoring

How to Use Telesto MAX10 FPGA Module

The following sections describe in detail how to use this module.

Hardware Accessories Required

Along with the module, you may need the items in the list below for easy and fast installation.

  1. USB A to Micro B cable.
  2. USB-Blaster II (JTAG programmer, Optional)
  3. DC Power supply (Optional)

Connection Diagram

This diagram should be used as a reference only. For detailed information, see Telesto’s schematics and mechanical dimensions at the end of this page. Details of individual connectors are as below.

USB Interface

The on board full speed USB controller helps a PC/Linux/Mac computer to communicate with this module. Use a USB A to Micro B cable to connect to a PC. By default, the module is powered by USB so make sure not to overcrowd unpowered USB hubs (the picture on the right shows USB Micro connector).

 

DC Power Supply

By default, the board is configured to use +5V supply from USB. So an external power is not required unless USB port is unable to supply enough current. USB 2.0 ports are only capable of providing enough current for the module for small designs which require less power. The current requirement for this board largely depends on your application. Please consult FPGA data sheet for more details on power requirements. If for any reason, an external power supply needs to be used for the board, the Power select jumper should be configured properly before connecting the power supply. Please refer to the marking on the board for more details. The external power supply should be in the range of +5 to +12V, with sufficient current rating.

Power Select

The “Power Select” header P2 is used to configure the power source for the board. Connect pins 1 and 2 to use USB power and connect pins 2 and 3 to use the external DC power.

Configuration Switch and Reset Button

Telesto features a DIP-Switches and Push-Button as shown below

SwitchPin Name
DIP-Switch (SW1)
1nCONFIG
2CONFIG_SEL

DIP-Switches:

DIP Switches are connected to FPGA pins H9 (nCONFIG) and H10 (CONFIG_SEL). nCONFIG and CONFIG_SEL pins are pulled up with 10K resistor.

nCONFIG is used to control the configuration cycle. ON to OFF transition will reset the FPGA and OFF to ON transition will trigger the FPGA configuration.

CONFIG_SEL pin is used to select the image to load the configuration. The image CFM0 is selected when this pin is OFF state and image CFM1 is selected when this pin is ON state. CFM0 and CFM1 are internal flash configuration images.

Reset Push-Button:

Telesto features a Push-button S1 normally meant to be used as “Reset” signal for designs running on FPGA. Push button S1 is connected to FPGA pin D9. Push-button S1 is active-high, and users need to enable FPGA’s internal Pulldown on the pin D9 to use the pushbutton correctly. This pushbutton can also be used for any other input, and is not just limited to be used as a Reset signal.

JTAG

JTAG connector provides access to FPGA’s JTAG pins. A USB-Blaster II cable can be used to for JTAG programming.

GPIOs

This device is equipped with a maximum 150 user IO pins that can be used for various custom applications. All user IOs  are length matched and can be used as differential pairs.

Bank wise IO Length Matching Details:

IO BankLength
Bank 2 IOs length matched to 1740 mils
Bank 3 IOs length matched to 1520 mils
Bank 4 IOs length matched to 1520 mils
Bank 7 IOs length matched to 1520 mils

Header P4

Pin No. On The Header10M50DA (F484) Pin No.Pin No. On The Header10M50DA (F484) Pin No.
1GND2VCC3V3
3VIN4GND
5AA16AA2
7Y18Y2
9Y310Y4
11AB212AB3
13W414W3
15V416V5
17Y518Y6
19AA520AB5
21U622U7
23W524W6
25AA626AA7
27AB628AB7
29R930P9
31V732V8
33W734W8
35Y736Y8
37Y1038AA10
39AA840AB8
41W942W10
43AA944AB9
45R1046P10
47V948V10
49GND50GND
51GND52GND
53R1254P12
55AB1056AB11
57R1158P11
59W1160Y11
61R1362P13
63AA1164AA12
65W1266W13
67AB1268AB13
69V1370W14
71Y1372Y14
73V1474W15
75AA1476AB15
77U1578V16
79AA1580Y16
81Y1982W18
83AB1684AA16
85W1786V17
87AB2188AA20
89GND90GND
91GND92GND
93VCC3V394VCC3V3
95VCC3V396VCC3V3

Header P5

Pin No. On The Header10M50DA (F484) Pin No.Pin No. On The Header10M50DA (F484) Pin No.
1ADC_CH12ADC_CH2
3VIN4GND
5ADC_CH36ADC_CH4
7U18V1
9ADC_CH510ADC_CH6
11T312U2
13ADC_CH714ADC_CH8
15T116T2
17R418R5
19P320R3
21A1022A11
23R124R2
25N326N2
27P128N1
29T530T6
31P432P5
33N834N9
35J1136H12
37J1238H13
39D1240C12
41C942B10
43C1044C11
45GND46GND
47GND48GND
49GND50GND
51GND52GND
53B854A9
55A856A7
57M858M9
59D1360E12
61B1162B12
63N464N5
65J1366H14
67E1468D15
69C1370C14
71A1272A13
73E1574E16
75B1476A14
77F1578F16
79C1780D17
81B1782C18
83A1784A18
85B1986C19
87A1988A20
89nSTATUS90VCC3V3
91nCONFIG92VCC3V3
93GND94GND
95GND96GND

* ADC_CH1 – ADC_CH8 pins are ADC pins.

FT2232H – 10M50DA (F484) FPGA Connection Details

FTDI Pin No.Pin Function (245 FIFO)10M50DA Pin No.
16D0B2
17D1B1
18D2A2
19D3A3
21D4A5
22D5A4
23D6B3
24D7B4
26RXF_NC4
27TXE_NB5
28RD_NC2
29WR_NC3
30SIWUAA6
32CLKOUTJ10
33OE#B7

Driver Installation

Windows

This product requires a driver to be installed for proper functioning when used with Windows. The D2XX driver can be downloaded from http://www.ftdichip.com/Drivers/D2XX.htm. Windows Users should download and run the latest WHQL Certified executable file that will prompt to install the FTDI CDM drivers.

Powering Up Telesto

Telesto is factory configured to be powered directly from USB port so make sure that you are using a USB port that can power the board properly. It is recommended to connect the board directly to the PC instead using a hub. It is practically very difficult to estimate the power consumption of the board, as it depends heavily on your design and the clock used. ALTERA provides tools to estimate the power consumption. In any case if power from USB is not enough for your application, external supply can be applied to the board. Jumper P2 should be set up properly (short pin 2-3) to use the board on external power. Telesto requires five different voltages, a 3.3V, a 2.5V, a 1.8V, a 1.2V, a 0.75V supplies and a 1.5V supply. On-board regulators derive these voltages from the USB/Ext power supply.

Programming Telesto MAX10 FPGA Module

The Telesto MAX10 FPGA Module can be programmed by two methods:

  1. Using external USB-Blaster II connected to JTAG header.
  2. Using Telesto’s onboard USB with OpenOCD.

Programming Telesto using USB-Blaster II and Quartus II Programmer

Telesto Max 10 FPGA Module features a JTAG connector which facilitates easy reprogramming of SRAM and internal flash through external JTAG programmer like “USB-Blaster II”. Programming Telesto using USB-Blaster requires “Quartus Programmer”. To program the FPGA SRAM, an “.sof” (SRAM object file) file is required and to program internal flash, a “.pof” (Programmer object file) file is required. In Quartus, the .sof and .pof files are generated automatically as part of compilation process. Please follow the steps below to program Telesto using USB-Blaster.

Step 1: Run Quartus Prime Programmer and set up the hardware by clicking “Hardware Setup” as shown below. Select the hardware as “USB-Blaster” or equivalent.

 

Step 2: Click “Close”. Next, double-click “Auto Detect”, select the device as applicable and click “OK”.

 

Step 3: Double-click “none” as shown below and select the “.sof/.pof” file to program Telesto with.

 

Step 4: Select the “Program/Configure” option and click “Start” to program the FPGA on Telesto.

 

Programming Telesto using OpenOCD

To program Telesto using OpenOCD using the on-board USB interface on Telesto, please refer to the article “Programming Telesto using OpenOCD” in our Knowledge Base: https://numato.com/kb/programming-telesto-using-openocd/

Technical Specifications

Parameter *ValueUnit
Basic Specifications
Number of GPIOs150 + 8 (Max)
On-board oscillator frequency (ASVMPLV-100.000MHZ-LC-T)100MHz
DDR3 Capacity2Gb
Power supply voltage (External)5 - 12V
FPGA Specifications
Supply voltage for core and periphery -0.5 - 1.63V
Supply voltage for input and output buffers -0.5 - 3.9 V
Supply voltage for ADC analog block-0.5 - 3.41V
Supply voltage for ADC digital block -0.5 - 1.63V

Mechanical Dimensions

Schematics

Telesto GPIO Easy Reference

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