AMD Kintex Ultrascale FPGA Board

The Neutron KU60 FPGA Development Board is a high-performance platform built around the AMD Kintex UltraScale XCKU060 FPGA, designed for demanding high-speed computing, networking, and signal-processing applications. Featuring 4GB ECC-enabled DDR4, dual QSPI configuration memory, multiple clock sources, high-speed SFP+ connectivity, GTH transceiver access, and versatile expansion through FMC+ HSPC, FMC HPC, and an M.2 slot, the board delivers exceptional flexibility for advanced development. With JTAG/USB programming, and programmable clock options, Neutron KU60 provides a robust and adaptable environment for prototyping and deployment.

• FPGA: AMD Kintex Ultrascale XCKU060-1FFVA1517I. Speed Grade -1.
• 5GB DDR4 SDRAM (72 Bit ECC) for reliable high-speed memory operation
• 512Mb (256 x 2) Dual QSPI flash for configuration
• Clocks:
  • 1 × 300MHz CMOS for DDR4
  • 1 × 200MHz CMOS for Fabric clock
  • 1 × 200MHz CMOS for system clock
• 2 × SFP+ cages supporting high-speed serial networking
• 2-lane GTH transceiver access via SMA connectors
• M.2 slot (M-key) for NVMe or compatible modules
• 1 × Gigabit Ethernet port for network connectivity
• FMC+ HSPC connector (VITA 57.4) for high-bandwidth expansion
• FMC HPC connector (VITA 57.1) for additional I/O expansion
• FPGA Programming & Debugging via JTAG and USB.
• Programmable clock available for GTH reference and M.2 interface requirements

• Data acquisition and processing
• Signal processing
• High-speed networking
• Embedded systems prototyping
• Scientific computing & research

1. 12V DC Power Supply.
2. AMD Platform Cable USB II JTAG debugger.
3. USB Type C cable.
4. Neutron KU60 FPGA Development Board

The board is configured to use power from DC power supply by connecting it to the External DC Jack. Please refer to the marking on the board for more details. The external power supply should be 12V, with sufficient current rating.

The KSZ9031RNX is a completely integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physical layer transceiver for transmission and reception of data. It provides the Reduced Gigabit Media Independent Interface (RGMII) for direct connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at 10/100/1000 Mbps.

The board uses an FTDI FT4232HL-REEL USB interface device.
Channel C of the FTDI is configured as a UART interface, and the associated signal connections are listed below.

Neutron KU60 development board features two SFP+ cages (Small form-factor hot-pluggable optical module transceivers), which can be used for optical fiber communication.

SFP0

SFP1

Note: The I²C lines from the SFP connectors are routed through an onboard I²C multiplexer shared with other peripherals on the board. Please refer to the I²C Multiplexer section of this user manual for details.

The board provides SMA connectors connected directly to the FPGA’s high-speed GTH transceiver banks. SMA connectors are routed to two GTH transceiver data lanes, and one SMA connector is routed to a GTH reference clock input.

These connectors allow the FPGA to interface with external high-speed serial data sources and sinks, as well as an external reference clock, for applications such as high-speed communication testing, protocol evaluation, and signal integrity measurements.

Neutron KU60 FPGA development board features a high speed, high pin-count FMC connector which can be used to provide additional features and capabilities to it using custom or commercial-off-the-shelf daughter boards. Apart from IOs, 8 GTX lanes are available via FMC connector for custom purposes.

FMC HPC BANKS A TO E

FMC HPC BANKS F TO K

Neutron KU60 development board features a FMC+ HSPC (High serial pin count) connector on the board that follows the ANSI/VITA 57.4 specification and provides a high-pin-count interface for FMC+ mezzanine cards.
The connector supports 16 FPGA GTH transceiver lane pairs, along with fabric-based differential I/O, enabling high-speed serial and parallel expansion through FMC+ modules.

FMC+ HSPC BANKS A TO E

FMC+ HSPC BANKS F TO K

FMC+ HSPC L , M, Z & Y

The Neutron board includes an M.2 female connector that supports PCI Express–based expansion modules, such as NVMe solid-state drives (SSDs).
The connector is interfaced directly to the FPGA’s, enabling high-speed storage and custom PCIe-based applications.

The Neutron board includes a Spartan-7 FPGA that acts as a configuration controller for the Kintex Ultrascale FPGA. The Spartan-7 is used to program the Kintex Ultrascale device via the SelectMAP configuration interface, enabling controlled and flexible configuration of the Kintex FPGA.

This architecture allows the Kintex Ultrascale FPGA to be configured and managed indirectly through the Spartan-7, supporting advanced configuration, boot, and system management use cases.

Contact us for more details about the system controller.

The bitstream can be generated for Neutron KU60 FPGA Development Board in Vivado by following the steps below:

Step 1: It is recommended to generate .bin bitstream file along with .bit bitstream file. Right Click on “Bitstream Settings”.

Step 2: Select “-bin_file*” option in the dialog window and Click “OK”.

Step 3: Finally click “Generate Bitstream”.

1. Ensure that switch SW3 (PGM SEL) is set to USB mode and Connect the USB Type-C cable to the FPGA board.

2. Click on “Auto connect” under hardware manager and it will automatically establish the connection.

Neutron KU60 FPGA Development Board features an onboard JTAG connector which facilitates easy reprogramming of SRAM and onboard SPI flash through JTAG programmer like “AMD Platform cable USB”. Following steps illustrate how to program FPGA on Neutron KU60 using JTAG.

Single QSPI Programming

A .bin or .mcs file is required for programming Neutron KU60 onboard QSPI flash.

Step 1: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 2: If the device is detected successfully, then select “Add Configuration Memory Device” after right clicking on the target device  “xcku060_0” or “xc7s50_1” as shown below.

Step 3: Select the memory device “mt25ql256-spi-x1_x2_x4”, then click OK.

Step 4: After completion of Step 3 the following dialog box will open. Click OK.

Step 5: Browse to the working .bin file or the .mcs file (whichever applicable) and click OK to program as shown below. If programming is successful, a confirmation message will be displayed.

Dual QSPI Programming

Step 1: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 2: If the device is detected successfully, then select “Add Configuration Memory Device” after right clicking on the target device  “xcku060_0” or “xc7s50_1” as shown below.

Step 3: Select the memory device “mt25ql256-spi-x1_x2_x4_x8”, then click OK.

Step 4: After completion of Step 3 the following dialog box will open. Click OK.

Step 5: Browse to the working .bin file or the .mcs file (whichever applicable) and click OK to program as shown below. If programming is successful, a confirmation message will be displayed.

Neutron IO length details

• The FMC HPC I²C interface is not functional.
• The FMC+ HSPC I²C interface is not functional.
• The programmable clock (SI5332H-D-GM1) can only be configured using external software. It will be shipped with a default frequency of 100 MHz on all six outputs (customizable based on requirements).