Xilinx Kintex 7 FPGA Boards

Nereid Kintex 7 PCI Express Development Board

788 views March 7, 2017 rohitsingh 0

Introduction

Nereid is an easy to use FPGA Development Board featuring Xilinx Kintex-7 FPGA with x4 PCIe interface and 4GB DDR3L SDRAM. This board features Xilinx XC7K160T– FBG676 FPGA. Other FPGA configurations are available at request. The board features High Pin Count (HPC) high speed FMC connector conforming to ANSI/VITA 57.1 Standard for the purpose of adding additional features to the board by using custom or commercial off-the-shelf daughter boards.

Applications:

  • Parallel Processing and Accelerators
  • Product Prototype Development
  • Development and Testing of custom embedded processors
  • Signal Processing
  • Communication Devices Development
  • Data Acquisition
  • Educational tool for Schools and Universities

Board features

  • FPGA: Kintex-7 XC7K160T in -1 FBG676 package (Other devices available at request)
  • 4 lane PCIe Gen2.0 (5GT/s)
  • 4GB DDR3L SODIMM SDRAM M471B5173CB0-YK0 or compatible
  • 128 Mb QSPI flash memory (N25Q128A13ESE40E) for Configuration and optional data storage
  • USB to UART serial converter
  • 1 x 100MHz CMOS oscillator, 1x 150MHz LVDS oscillator for users
  • 1 x 150MHz LVDS oscillator for GTP
  • Maximum 174 IOs for user defined purposes on ANSI/VITA 57.1 Standard compliant FMC HPC connector
  • 4x GTP lanes upto 6.6Gbps on ANSI/VITA 57.1 Standard compliant FMC HPC connector
  • On-board voltage regulators for single power rail operation
  • Can be powered from PCIe slot or from an external power supply
  • JTAG header for programming and debugging
  • All differential pairs are length matched on the board
  • 1 RGB LED for custom use

 

How to Use Nereid Kintex 7 PCI Express Development Board

Hardware Accessories Required

Along with the board, following accessories are required for easy and fast installation.

  1. 12 V DC Power Supply (not needed if the board is inserted into a motherboard)
  2. A Xilinx Platform Cable USB II compatible JTAG programmer
  3. USB Male A to Micro B cable (optional)

Connection Diagram

This diagram should be used as a reference only. For detailed information, see Nereid’s schematics and mechanical dimensions at the end of this page. Details of individual connectors are as below.

Power

Nereid requires +12V power supply to function properly. Nereid can be supplied power in 3 ways:

  1. External +12V power via DC Barrel Jack Connector
  2. External +12V power via 3×2 PCIe Power Connector.
  3. Via Motherboard when Nereid is plugged into a PCIe slot that is capable of powering Nereid

Current requirement for this board largely depends on your application. The Nereid module works on power supply of 1 A of current for simple applications. However, a power supply 2 A of current is recommended for a smooth running of bigger applications. Please consult FPGA data sheet for more details on power requirements.

USB Serial Bridge

USB Serial Bridge can be used to interface with PC using serial interface. It is primarily used to output debug information or as a console for the design running on the board. A Micro USB type cable should be used to connect Nereid to host PC. An FT234 is used as the USB-Serial Bridge IC. The USB-Serial interface features hardware flow control using RTS and CTS signals, in case users need to use hardware flow control. An extra signal CBUS0 from FT234X is also connected to FPGA, which can be used as host-controlled GPIO or can be used for other purpose.

Heat Sink

A Heat Sink (Digikey Part Number: 345-1147-ND) comes factory-installed with Nereid to provide for heat dissipation for the Kintex-7 FPGA on board. A header is provided to optionally connect a fan (not factory installed) for forced-cooling. The fan’s speed is controlled by the FAN_PWM signal connected to FPGA IO location J25, and the signal is pulled up by default, which means unless actively driven to 0 or controlled via PWM, the fan will run at maximum speed.

JTAG

JTAG connector allows the FPGA’s JTAG registers to be accessed using a JTAG cable compatible with Xilinx Platform Cable USB. Use this header to attach JTAG cable for programming and debugging.

 

SODIMM Memory Slot

Nereid features a SODIMM Memory Slot factory-populated with 4GB DDR3L SDRAM. Only compatible modules should be inserted into this slot.

RGB LED

 

Nereid features one RGB LED which can be used for custom or debug purposes. The LED is wired in active-low configuration.

 

JTAG Chain Configuration

JTAG chain can be modified using jumper P2 near JTAG header.

Following diagram shows JTAG chain configuration:

Nereid has automatic FMC detection using PRSNT_M2C_L signal from FMC. Normally, when an FMC board is not connected, the Nereid’s onboard circuitry will automatically close the JTAG chain keeping FMC out from the chain, so no user intervention is required. But, still jumper P2 has been provided as redundant backup to close the JTAG chain in case the automatic circuitry doesn’t work due to non-compliant FMC modules connected to Nereid, or any or unforeseen reasons.

Configuration Mode Switch

FPGA startup configuration mode can be selected using switch S1.

Sliding it to ON puts FPGA in “JTAG” configuration mode. Sliding it to OFF puts the FPGA to “Master SPI” configuration mode.

 

Reset Switch

Nereid features a Push-button S2 normally meant to be used as “Reset” signal for designs running on FPGA. Push-button S2 is connected to FPGA pin C26. Push-button S2 is active-high, and users need to enable FPGA’s internal Pulldown on the pin C26 to use the pushbutton correctly. This pushbutton can also be used for any other input, and is not just limited to be used as Reset signal.

FMC VADJ Power Supply

VADJ Power Supply for FMC Bank A is configurable via jumpers J3. Following are the jumper configurations for different voltages for VADJ supply.

Jumper on J3 HeaderFMC VADJ Power Supply (Volts)
No jumper anywhere3.3
1 - 22.5
3 - 41.8
5 - 6 1.5
7 - 81.2

 

PCIe x4 Edge Connector

PCI Express 2.0 4-lane edge-connector on Nereid can be used to interface with host PCs via PCI Express protocol. Each lane is capable of 5 GT/s resulting in maximum theoretical data transfer rate of 2 GB/s for all 4 lanes combined.

PCI Express x4 Edge Connector
Signal NameKintex-7 (FBG676) Pin
REFCLK_PK6
REFCLK_NK5
PCIE_TX0_PH1
PCIE_TX0_NH2
PCIE_TX1_PK1
PCIE_TX1_NK2
PCIE_TX2_PM1
PCIE_TX2_NM2
PCIE_TX3_PP1
PCIE_TX3_NP2
PCIE_RX0_PJ3
PCIE_RX0_NJ4
PCIE_RX1_PL3
PCIE_RX1_NL4
PCIE_RX2_PN3
PCIE_RX2_NN4
PCIE_RX3_PR3
PCIE_RX3_NR4
PCIE_PERSTnE21

FMC Connector

Nereid features a high speed, high pin-count FMC connector which can be used to provide additional features and capabilities to it using custom or commercial off-the-shelf daugther boards. Apart from IOs, 4 GTX lanes are available via FMC connector for custom purpose.

FMC Banks A to D

AFMC Pin NameKintex-7 FBG676 PinBFMC Pin NameKintex-7 FBG676 PinCFMC Pin NameKintex-7 FBG676 PinDFMC Pin NameKintex-7 FBG676 Pin
A1GNDGNDB1CLK_DIRD23C1GNDGNDD1PG_C2MD26
A2DP1_M2C_PE4B2GNDGNDC2DP0_C2M_PF2D2GNDGND
A3DP1_M2C_NE3B3GNDGNDC3DP0_C2M_NF1D3GNDGND
A4GNDGNDB4DP9_M2C_PNCC4GNDGNDD4GBTCLK0_M2C_PF6
A5GNDGNDB5DP9_M2C_NNCC5GNDGNDD5GBTCLK0_M2C_NF5
A6DP2_M2C_PC4B6GNDGNDC6DP0_M2C_PG4D6GNDGND
A7DP2_M2C_NC3B7GNDGNDC7DP0_M2C_NG3D7GNDGND
A8GNDGNDB8DP8_M2C_PNCC8GNDGNDD8LA01_P_CCY23
A9GNDGNDB9DP8_M2C_NNCC9GNDGNDD9LA01_N_CCAA24
A10DP3_M2C_PB6B10GNDGNDC10LA06_PY25D10GNDGND
A11DP3_M2C_NB5B11GNDGNDC11LA06_NY26D11LA05_PW25
A12GNDGNDB12DP7_M2C_PNCC12GNDGNDD12LA05_NW26
A13GNDGNDB13DP7_M2C_NNCC13GNDGNDD13GNDGND
A14DP4_M2C_PNCB14GNDGNDC14LA10_PV21D14LA09_PW20
A15DP4_M2C_NNCB15GNDGNDC15LA10_NW21D15LA09_NY21
A16GNDGNDB16DP6_M2C_PNCC16GNDGNDD16GNDGND
A17GNDGNDB17DP6_M2C_NNCC17GNDGNDD17LA13_PK20
A18DP5_M2C_PNCB18GNDGNDC18LA14_PJ18D18LA13_NJ20
A19DP5_M2C_NNCB19GNDGNDC19LA14_NJ19D19GNDGND
A20GNDGNDB20GBTCLK1_M2C_PD6C20GNDGNDD20LA17_P_CCE18
A21GNDGNDB21GBTCLK1_M2C_ND5C21GNDGNDD21LA17_N_CCD18
A22DP1_C2M_PD2B22GNDGNDC22LA18_P_CCF17D22GNDGND
A23DP1_C2M_ND1B23GNDGNDC23LA18_N_CCE17D23LA23_PC17
A24GNDGNDB24DP9_C2M_PNCC24GNDGNDD24LA23_NC18
A25GNDGNDB25DP9_C2M_NNCC25GNDGNDD25GNDGND
A26DP2_C2M_PB2B26GNDGNDC26LA27_PG15D26LA26_PJ15
A27DP2_C2M_NB1B27GNDGNDC27LA27_NF15D27LA26_NJ16
A28GNDGNDB28DP8_C2M_PNCC28GNDGNDD28GNDGND
A29GNDGNDB29DP8_C2M_NNCC29GNDGNDD29TCK
A30DP3_C2M_PA4B30GNDGNDC30SCLC21D30TDIR7
A31DP3_C2M_NA3B31GNDGNDC31SDAB21D31TDO
A32GNDGNDB32DP7_C2M_PNCC32GNDGNDD323P3VAUXVCC3V3
A33GNDGNDB33DP7_C2M_NNCC33GNDGNDD33TMS
A34DP4_C2M_PNCB34GNDGNDC34GA0GNDD34TRST_LNC
A35DP4_C2M_NNCB35GNDGNDC3512P0VVCC12V0D35GAIGND
A36GNDGNDB36DP6_C2M_PNCC36GNDGNDD363P3VVCC3V3
A37GNDGNDB37DP6_C2M_NNCC3712P0VVCC12V0D37GNDGND
A38DP5_C2M_PNCB38GNDGNDC38GNDGNDD383P3VVCC3V3
A39DP5_C2M_NNCB39GNDGNDC393P3VVCC3V3D39GNDGND
A40GNDGNDB40RES0NCC40GNDGNDD403P3VVCC3V3

FMC Banks E to H

EFMC Pin NameKintex-7 FBG676 PinFFMC Pin NameKintex-7 FBG676 PinGFMC Pin NameKintex-7 FBG676 PinHFMC Pin NameKintex-7 FBG676 Pin
E1GNDGNDF1PG_M2CE26G1GNDGNDH1VREF_A_M2CNC
E2HA01_P_CCN21F2GNDGNDG2CLK1_M2C_PAC23H2PRSNT_M2C_LB26
E3HA01_N_CCN22F3GNDGNDG3CLK1_M2C_NAC24H3GNDGND
E4GNDGNDF4HA00_P_CCP23G4GNDGNDH4CLK0_M2C_PY22
E5GNDGNDF5HA00_N_CCN23G5GNDGNDH5CLK0_M2C_NAA22
E6HA05_PR18F6GNDGNDG6LA00_P_CCAA23H6GNDGND
E7HA05_NP18F7HA04_PN19G7LA00_N_CCAB24H7LA02_PAD26
E8GNDGNDF8HA04_NM20G8GNDGNDH8LA02_NAE26
E9HA09_PN18F9GNDGNDG9LA03_PAA25H9GNDGND
E10HA09_NM19F10HA08_PU19G10LA03_NAB25H10LA04_PAD25
E11GNDGNDF11HA08_NU20G11GNDGNDH11LA04_NAE25
E12HA13_PU24F12GNDGNDG12LA08_PU26H12GNDGND
E13HA13_NU25F13HA12_PT24G13LA08_NV26H13LA07_PV23
E14GNDGNDF14HA12_NT25G14GNDGNDH14LA07_NV24
E15HA16_PR25F15GNDGNDG15LA12_PM17H15GNDGND
E16HA16_NP25F16HA15_PP24G16LA12_NL18H16LA11_PL19
E17GNDGNDF17HA15_NN24G17GNDGNDH17LA11_NL20
E18HA20_PM25F18GNDGNDG18LA16_PT18H18GNDGND
E19HA20_NL25F19HA19_PK25G19LA16_NT19H19LA15_PU17
E20GNDGNDF20HA19_NK26G20GNDGNDH20LA15_NT17
E21HB03_PJ13F21GNDGNDG21LA20_PK16H21GNDGND
E22HB03_NH13F22HB02_PH14G22LA20_NK17H22LA19_PH16
E23GNDGNDF23HB02_NG14G23GNDGNDH23LA19_NG16
E24HB05_PB15F24GNDGNDG24LA22_PC19H24GNDGND
E25HB05_NA15F25HB04_PB14G25LA22_NB19H25LA21_PD19
E26GNDGNDF26HB04_NA14G26GNDGNDH26LA21_ND20
E27HB09_PD14F27GNDGNDG27LA25_PF19H27GNDGND
E28HB09_ND13F28HB08_PE13G28LA25_NE20H28LA24_PD15
E29GNDGNDF29HB08_NE12G29GNDGNDH29LA24_ND16
E30HB13_PB12F30GNDGNDG30LA29_PE15H30GNDGND
E31HB13_NB11F31HB12_PB10G31LA29_NE16H31LA28_PG17
E32GNDGNDF32HB12_NA10G32GNDGNDH32LA28_NF18
E33HB19_PA9F33GNDGNDG33LA31_PG19H33GNDGND
E34HB19_NA8F34HB16_PD9G34LA31_NF20H34LA30_PH17
E35GNDGNDF35HB16_ND8G35GNDGNDH35LA30_NH18
E36HB21_PH9F36GNDGNDG36LA33_PL17H36GNDGND
E37HB21_NH8F37HB20_PJ11G37LA33_NK18H37LA32_PH19
E38GNDGNDF38HB20_NJ10G38GNDGNDH38LA32_NG20
E39VADJVCCVADJF39GNDGNDG39VADJVCCVADJH39GNDGND
E40GNDGNDF40VADJVCCVADJG40GNDGNDH40VADJVCCVADJ

FMC Banks J to K

JFMC Pin NameKintex-7 FBG676 PinKFMC Pin NameKintex-7 FBG676 Pin
J1GNDGNDK1VREF_B_M2CH11/C13
J2CLK3_BIDIR_PR21K2GNDGND
J3CLK3_BIDIR_NP21K3GNDGND
J4GNDGNDK4CLK2_BIDIR_PR22
J5GNDGNDK5CLK2_BIDIR_NR23
J6HA03_PAD23K6GNDGND
J7HA03_NAD24K7HA02_PAB22
J8GNDGNDK8HA02_NAC22
J9HA07_PR16K9GNDGND
J10HA07_NR17K10HA06_PP16
J11GNDGNDK11HA06_NN17
J12HA11_PP19K12GNDGND
J13HA11_NP20K13HA10_PT20
J14GNDGNDK14HA10_NR20
J15HA14_PR26K15GNDGND
J16HA14_NP26K16HA17_P_CCM21
J17GNDGNDK17HA17_N_CCM22
J18HA18_PN26K18GNDGND
J19HA18_NM26K19HA21_PM24
J20GNDGNDK20HA21_NL24
J21HA22_PT22K21GNDGND
J22HA22_NT23K22HA23_PU22
J23GNDGNDK23HA23_NV22
J24HB01_PF14K24GNDGND
J25HB01_NF13K25HB00_P_CCE10
J26GNDGNDK26HB00_N_CCD10
J27HB07_PG10K27GNDGND
J28HB07_NG9K28HB06_P_CCC12
J29GNDGNDK29HB06_N_CCC11
J30HB11_PA13K30GNDGND
J31HB11_NA12K31HB10_PC9
J32GNDGNDK32HB10_NB9
J33HB15_PE11K33GNDGND
J34HB15_ND11K34HB14_PF9
J35GNDGNDK35HB14_NF8
J36HB18_PG12K36GNDGND
J37HB18_NF12K37HB17_P_CCG11
J38GNDGNDK38HB17_N_CCF10
J39VIO_B_M2CFMC_VIO_B_M2CK39GNDGND
J40GNDGNDK40VIO_B_M2CFMC_VIO_B_M2C

USB-Serial Bridge Driver

Installing Driver for USB Serial Converter on Windows

This board requires a driver to be installed to use USB serial converter, for board’s proper functioning when used with Windows. Ideally, Windows should automatically search and install correct driver for Nereid via Windows Update. For manual installation, the FTDI VCP drivers are available for download from http://www.ftdichip.com/.

Generating Bitstream Using Vivado

The PCI Express specification requires cards to be ready for link training within 100 ms after the host PC’s power supply is stable.

Following constraints need to be added to the xdc file before synthesising, implementing and generating bitstream for a PCI Express design. These can be safely ignored if PCI Express interface is not used in the design.

set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

Step 1: It is recommended to generate .bin bitstream file along with .bit bitstream file. Click “Bitstream Settings”.vivado_bitstream_settings_location

Step 2: Select “-bin_file*” option in the dialog window and Click OK.

vivado_bitstream_settings

Step 3: Finally click “Generate Bitstream”.

vivado_generate_bitstream

 

Programming Nereid Using JTAG

Nereid Kintex-7 PCI Express FPGA Board features an on-board JTAG connector which facilitates easy reprogramming of SRAM and on-board SPI flash through JTAG programmer like “Xilinx Platform cable USB”. Following steps illustrate how to program FPGA on Nereid using JTAG.

Step 1: Connect Xilinx Platform cable USB to Nereid using JTAG cable. Power up Nereid.

Step 2: Open Vivado Project. Click on “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

vivado_open_hardware_manager

Step 3: If the device is successfully detected, then right click on the “xc7k160t_0”. Select “Program Device” as shown below.

vivado_program_device

Step 4: In the dialog window which opens up, Vivado automatically chooses correct bitstream file if the design was synthesized, implemented and bitstream gennerated successfully. If needed, browse to the bitstream which needs to be programmed to FPGA. Finally click “Program”.

vivado_program_device_2

As soon as “Program” is clicked, a green colored LED (D1) on Nereid should light up, indicating that programming process is going on. This LED will turn off when configuration is complete.

 

 

 

Programming QSPI Flash using Vivado

A .bin or .mcs file is required for programming Nereid’s on-board QSPI flash.

Step 1: Open Vivado Project. Click on “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window.

vivado_open_hardware_manager

Step 2: If the device is successfully detected, then right click on the “xc7k160t_0”. Select “Add Configuration Memory Device” as shown below.

vivado_add_configuration_memory_device

Step 3: Select the memory device “n25q128-3.3v-spi-x1_x2_x4”, then click OK.

vivado_select_memory_device

Step 4: After completion of Step 3 the following dialog box will open. Click OK.

vivado_program_memory_now_option

Step 5: Browse to the working .bin file or the .mcs file (whichever applicable) and click OK to program as shown below. If programming is successful, a confirmation message will be displayed.

vivado_program_memory

 

Technical Specifications

Parameter *ValueUnit
Basic Specifications
Number of GPIOs (Max) 174
On-board Oscillator Frequency (ASEM1-
100.000MHZ-LC-T)
100 (x1)MHz
On-board Oscillator Frequency (ASVMPLV-
150.000MHZ-L-T)(1 for GTP, 1 for User purpose)
150 (x2)MHz
DDR3 (M471B5173CB0-YK0)4 (x1)GB
SPI Flash Memory (N25Q128A13ESE40E)128Mb
Power supply voltage (External) 12V
FPGA Specifications
Internal supply voltage relative to GND-0.5 to 1.32V
Auxiliary supply voltage relative to GND -0.5 to 3.75V
Output drivers supply voltage relative to GND -0.5 to 3.75V
Connector Header Specifications (0459704715)
Number of Positions400
Number of Rows 10
Height above Board8.05mm
Pitch1.27mm
Mated Stacking Height10, 10.5, 11, 11.5, 12.5, 13, 15mm
Mated Receptacle on Nereid module0459714515

Mechanical Dimensions

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