Xilinx Kintex 7 FPGA Boards

Nereid is an easy to use FPGA Development Board featuring Xilinx Kintex-7 FPGA with x4 PCIe interface and 4GB DDR3L SDRAM. This board features Xilinx XC7K160T– FBG676 FPGA. Other FPGA configurations are available at request. The board features High Pin Count (HPC) high-speed FMC connector conforming to ANSI/VITA 57.1 Standard for the purpose of adding additional features to the board by using custom or commercial off-the-shelf daughter boards.

Applications:

• Parallel Processing and Accelerators
• Product Prototype Development
• Development and Testing of custom embedded processors
• Signal Processing
• Communication Devices Development
• Data Acquisition
• Educational tool for Schools and Universities

Board features

• FPGA: Kintex-7 XC7K160T in -1 FBG676 package (Other devices available at request)
• 4 lane PCIe Gen2.0 (5GT/s)
• 4GB DDR3L SODIMM SDRAM M471B5173CB0-YK0 or compatible
• 128 Mb QSPI flash memory (N25Q128A13ESE40E) for Configuration and optional data storage
• USB to UART serial converter
• 1 x 100MHz CMOS oscillator, 1x 150MHz LVDS oscillator for users
• 1 x 150MHz LVDS oscillator for GTX
• Maximum 174 IOs for user-defined purposes on ANSI/VITA 57.1 Standard compliant FMC HPC connector
• 4x GTX lanes up to 6.6Gbps on ANSI/VITA 57.1 Standard compliant FMC HPC connector
• On-board voltage regulators for single power rail operation
• Can be powered from PCIe slot or from an external power supply
• JTAG header for programming and debugging
• All differential pairs are length matched on the board
• 1 RGB LED for custom use

Along with the board, the following accessories are required for easy and fast installation.

1. 12 V DC Power Supply (not needed if the board is inserted into a motherboard)
2. A Xilinx Platform Cable USB II compatible JTAG programmer
3. USB Male A to Micro B cable (optional)

Nereid requires a +12V power supply to function properly. Nereid can be supplied power in 3 ways:

1. External +12V power via DC Barrel Jack Connector
2. External +12V power via 3×2 PCIe Power Connector.
3. Via Motherboard when Nereid is plugged into a PCIe slot that is capable of powering Nereid

The current requirement for this board largely depends on your application. The Nereid module works on a power supply of 1 A of current for simple applications. However, a power supply 2 A of current is recommended for a smooth running of bigger applications. Please consult the FPGA datasheet for more details on power requirements.

USB Serial Bridge can be used to interface with PC using the serial interface. It is primarily used to output debug information or as a console for the design running on the board. A Micro USB type cable should be used to connect Nereid to host PC. An FT234 is used as the USB-Serial Bridge IC. The USB-Serial interface features hardware flow control using RTS and CTS signals, in case users need to use hardware flow control. An extra signal CBUS0 from FT234X is also connected to FPGA, which can be used as host-controlled GPIO or can be used for other purposes.

A Heat Sink (Digikey Part Number: 345-1147-ND) comes factory-installed with Nereid to provide for heat dissipation for the Kintex-7 FPGA onboard. A header is provided to optionally connect a fan (not factory installed) for forced-cooling. The fan’s speed is controlled by the FAN_PWM signal connected to FPGA IO location J25, and the signal is pulled up by default, which means unless actively driven to 0 or controlled via PWM, the fan will run at maximum speed.

JTAG connector allows the FPGA’s JTAG registers to be accessed using a JTAG cable compatible with Xilinx Platform Cable USB. Use this header to attach JTAG cable for programming and debugging.

Nereid features a SODIMM Memory Slot factory-populated with 4GB DDR3L SDRAM. Only compatible modules should be inserted into this slot.

Nereid features one RGB LED which can be used for custom or debug purposes. The LED is wired in the active-low configuration.

JTAG chain can be modified using jumper P2 near JTAG header.

Following diagram shows JTAG chain configuration:

Nereid has automatic FMC detection using the PRSNT_M2C_L signal from FMC. Normally, when an FMC board is not connected, the Nereid’s onboard circuitry will automatically close the JTAG chain keeping FMC out from the chain, so no user intervention is required. But, still, jumper P2 has been provided as a redundant back up to close the JTAG chain in case the automatic circuitry doesn’t work due to non-compliant FMC modules connected to Nereid, or any or unforeseen reasons.

FPGA startup configuration mode can be selected using switch S1.

Sliding it to ON puts FPGA in the “JTAG” configuration mode. Sliding it to OFF puts the FPGA to the “Master SPI” configuration mode.

Nereid features a Push-button S2 normally meant to be used as a “Reset” signal for designs running on FPGA. Push-button S2 is connected to FPGA pin C26. Push-button S2 is active-high, and users need to enable FPGA’s internal Pulldown on the pin C26 to use the pushbutton correctly. This pushbutton can also be used for any other input and is not just limited to be used as a Reset signal.

VADJ Power Supply for FMC Bank A is configurable via jumpers J3. The following are the jumper configurations for different voltages for the VADJ supply.

PCI Express 2.0 4-lane edge-connector on Nereid can be used to interface with host PCs via PCI Express protocol. Each lane is capable of 5 GT/s resulting in a maximum theoretical data transfer rate of 2 GB/s for all 4 lanes combined.

PCI Express x4 Edge Connector

Nereid features a high speed, high pin-count FMC connector which can be used to provide additional features and capabilities to it using custom or commercial off-the-shelf daughter boards. Apart from IOs, 4 GTX lanes are available via FMC connector for custom purposes.

FMC Banks A to D

FMC Banks E to H

FMC Banks J to K

The PCI Express specification requires cards to be ready for link training within 100 ms after the host PC’s power supply is stable.

The following constraints need to be added to the xdc file before synthesizing, implementing and generating a bitstream for a PCI Express design. These can be safely ignored if the PCI Express interface is not used in the design.

set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

Step 1: It is recommended to generate a .bin bitstream file along with .bit bitstream file. Click “Bitstream Settings”.

Step 2: Select the “-bin_file*” option in the dialog window and click OK.

Step 3: Finally click “Generate Bitstream”.

Nereid Kintex-7 PCI Express FPGA Board features an onboard JTAG connector that facilitates easy reprogramming of SRAM and onboard SPI flash through JTAG programmer like “Xilinx Platform cable USB”. The following steps illustrate how to program FPGA on Nereid using JTAG.

Step 1: Connect Xilinx Platform cable USB to Nereid using JTAG cable. Power up Nereid.

Step 2: Open Vivado Project. Click on “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 3: If the device is successfully detected, then right-click on the “xc7k160t_0”. Select “Program Device” as shown below.

Step 4: In the dialog window which opens up, Vivado automatically chooses the correct bitstream file if the design was synthesized, implemented and bitstream generated successfully. If needed, browse to the bitstream which needs to be programmed to FPGA. Finally click “Program”.

As soon as “Program” is clicked, a green colored LED (D1) on Nereid should light up, indicating that the programming process is going on. This LED will turn off when the configuration is complete.

A .bin or .mcs file is required for programming Nereid’s onboard QSPI flash.

Step 1: Open Vivado Project. Click on “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window.

Step 2: If the device is successfully detected, then right-click on the “xc7k160t_0”. Select “Add Configuration Memory Device” as shown below.

Step 3: Select the memory device “n25q128-3.3v-spi-x1_x2_x4”, then click OK.

Step 4: After completion of Step 3 the following dialog box will open. Click OK.

Step 5: Browse to the working .bin file or the .mcs file (whichever applicable) and click OK to program as shown below. If programming is successful, a confirmation message will be displayed.

Download Nereid XDC Constraints For Vivado

NereidV4.2 Schematics