Xilinx Artix 7 FPGA Boards

HSFPX002 is an easy to use FPGA module featuring the Xilinx Artix 7 FPGA with total size of 24Gb DDR3 SDRAM. This board contains the Xilinx XC7A200T– FBG676 FPGA. This board features an Edge Rate® Rugged High-Speed Male connector, so this board works with the carrier boards (like Numato Lab’s HSFPX00X carrier board) that feature Edge Rate® Rugged High-Speed female connectors. This board has the FT601 IC for the configuration and communication between FPGA and USB host.

• FPGA: Artix XC7A200T in FBG676 package
• DDR3: 1x8Gb DDR3 (MT41K1G8SN-125:A) & two combined 512x16Mb DDR3 (MT41K512M16HA-125:A TR)
• Flash memory: 512 Mb Quad SPI flash memory (S25FL512SDSBHV210/IS25LP512M-RHLE)
• 1 x 100MHz CMOS oscillator
• 4x Edge Rate® Rugged High-Speed Male connectors
• 8 GTP lanes (up to 6.6 GT/s)
• FTDI FT601 for FPGA and Host communication
• Onboard voltage regulators for single-power rail operation
• 1 Bi-color LED for custom use
• Maximum IOs for user-defined purposes
  • FPGA – 96 differential I/O pairs

• Product Prototype Development
• Accelerated computing integration
• Memory Intensive FPGA development
• Data Acquisition
• Educational tool for Schools and Universities

The following sections describe in detail how to use this module.

This diagram should be used as a reference only. For detailed information, see HSFPX002’s schematics and mechanical dimensions at the end of this page. Details of individual connectors are as shown below.

HSFPX002 features one Bi-color LED which can be used for custom or debug purposes.

This device is equipped with a maximum 96 user IO pins that can be used for various custom applications. All user IOs are length matched and can be used as differential pairs.

HDL design needs to be converted to bitstream before it can be programmed to FPGA. Once the HDL is synthesized, it is easy to create a binary bitstream out of it. The bitstream can be generated for HSFPX002 in Vivado by following the steps below:

Step 1: It is recommended to generate .bin bitstream file along with .bit bitstream file. Right Click on “Bitstream Settings”.

Step 2: Select “-bin_file*” option in the dialog window and Click “OK”.

Step 3: Finally click “Generate Bitstream”.

To configure HSFPX002 Module using JTAG, a carrier board is required such as Numato Lab’s HSFPX00X board which features a JTAG connector which facilitates easy reprogramming of SRAM and on-board SPI flash through JTAG programmer like “XILINX Platform Cable USB”. Programming HSFPX002 using JTAG requires “XILINX Vivado Hardware Manager” software which is bundled with XILINX Vivado Design Suite. To program the SPI flash we need a “.mcs/.bin” file that needs to be generated from the “.bit” file. Steps for generating “.mcs/.bin” file are as below. Programming FPGA SRAM does not require a “.mcs/.bin” file to be generated.

Step 1: By using JTAG cable, connect Xilinx platform cable USB to HSFPX002 and power it up.

Step 2: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 3: If the device is detected successfully, to program the device, right click on the target device “xc7a200t_0” and select “Program Device” as shown below.

Step 4: In the dialog window which opens up, Vivado automatically chooses correct bitstream file if the design was synthesized, implemented and if the bitstream was generated successfully. If needed, browse to the bitstream which needs to be programmed to FPGA. Finally, click “Program”.

The screenshots shown in the following steps are captured from the Vivado Design Suite 2018.2.

Step 1: Open Xilinx Vivado Hardware Manager. Connect the board, click “Generate Memory Configuration File….” from “Tools” menu. “Write Memory Configuration File” pop up window will open.

Step 2: Select the ‘Format’ and Configuration Memory Part as shown below. Choose the format as MCS/BIN/HEX depending on your requirement. Now, click “OK”.

Step 3: Browse to the path where you wish to save the Configuration File and type the file name as “sample.bin” (or any name as per your wish/requirement) to save the memory configuration file (the format of the file may change depending on your “Format”). Select the “Load bitstream files” under the ”Options” tab and browse to the “.bit” file we already generated then click “OK” to generate memory configuration file.

A .bin or .mcs file is required for programming HSFPX002’s onboard QSPI flash.

Step 1: Open the Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 2: If the device is detected successfully, it will be displayed as shown in the image below. To add Configuration Memory Device, right-click on the target device “xc7a200t_0” and select “Add Configuration Memory Device” as shown below.

Step 3: Select the memory device “is25lp512m-spi-x1_x2_x4”, then click OK.

Step 4: Browse to the working .bin file or the .mcs file (whichever is applicable) and click OK to program as shown below. If programming is successful, a confirmation message will be displayed.

* All parameters considered nominal. Numato Systems Pvt Ltd reserves the right to modify products without notice.

HSFPX002 XDC File for Vivado

HSFPX002 Schematics

HSFPX002 ERM Connector Easy Reference