EagleCore ZU-Plus MPSoC SOM

The EagleCore ZU-Plus MPSoC SOM, which uses the part number XCZU3TEG-1SFVC784I, belongs to the UltraScale MPSoC family developed by AMD Xilinx. This series also includes compatible part numbers such as XCZU3TCG-1SFVC784I, XCZU3CG-1SFVC784I, and XCZU3EG-1SFVC784I. These SoCs combine the processing power of multiple ARM Cortex-A processors with the programmable logic fabric of a field-programmable gate array (FPGA), offering robust performance and flexibility for a wide range of applications.

Additionally, the EagleCore ZU-Plus MPSoC SOM includes RTC (Real-Time Clock) functionality, ensuring precise timekeeping for applications requiring accurate time management. This combination of ARM processing capabilities, FPGA programmable logic, and RTC functionality makes it particularly well-suited for fields where high performance and versatility are crucial.

Xilinx provides a comprehensive development ecosystem, including the Vivado Design Suite and the Vitis unified software platform, which allows developers to effectively leverage both the ARM and FPGA components and PetaLinux designed for building, customizing, and deploying embedded Linux systems.

• Device: Zynq UltraScale+™ MPSoC (XCZU3TEG-1SFVC784I)
• SDRAM – DDR4
• Oscillator: 33.33 MHz (PS), 100MHz (PL)
• eMMC: 8 GB Storage (expandable up to 64 GB)
• Flash Memory: 1 Gb SPI flash memory (MT25QU01GBBB8E12-0AAT)
• 1 x Gigabit Ethernet PHY
• OTG PHY
• EEPROM
• 8 x High speed transceiver lanes
• 4 x Razor Beam LSHM Series Samtec Connectors
• Programming & Debugging: JTAG programming
• 1 RGB LED for custom use
• IOs for user-defined purposes XCZU3TEG & XCZU3TCG
  • HP –  46 IOs
  • HD –  52 IOs
  • MIO – 15 IOs
• IOs for user-defined purposes XCZU3EG & XCZU3CG
  • HP –  94 IOs
  • HD –  52 IOs
  • MIO – 15 IOs

• Product Prototype Development
• Accelerated computing integration
• Custom Embedded platform
• Signal Processing
• Communication devices development
• Educational tool for Schools and Universities

Note: PL CLK won’t be available when user changes the voltage of PL bank 66 to 1.2 V.

The EagleCore ZU-Plus MPSoC SOM have a dedicated Done LED (D1) on the module.

EagleCore ZU-Plus MPSoC SOM includes 3 DDR4 chip with each having 1GB of memory and delivers enhanced memory bandwidth. EagleCore SOM uses micron MT40A512M16TB-062E:R memory with 2 DDR4 chips connected to the PS side and one in PL end. DDR4 on PS can offer data transfer rate of 2400 Mb/s, while the PL side can provide up to 1066 Mb/s.

PS DDR Pin Assignment

PL DDR Pin Assignment

PL DDR Clock pin Assignment

Note: PL DDR4  is compatible only for the part numbers XCZU3CG and XCZU3EG.

The Eaglecore ZU-Plus MPSoC SOM has 1 Gb of Quad bit SPI flash memory and uses the part number MT25QU01GBBB8E12-0AAT. It is a serial NOR flash which operates at the voltage of 1.8 V. It is connected to QSPI controller of the PS and serves as the primary boot device.

EagleCore ZU-Plus MPSoC have micro-SD card feature that can be incorporated in the carrier board. SD Card can be used to store non-volatile external memory. It is directly connected to the SD1 controller of the PS MIO bank  and operates at 3.3 V.

Note: This option is available upon customer request.

The EagleCore ZU-Plus MPSoC SOM accommodates 8 Gb of eMMC flash memory having the part number SDINBDG4-8G for additional storage, with the option to expand it up to 64 GB. It operates at a voltage level of 1.8 V and is connected to SD0 controller of the PS MIO bank.

EagleCore ZU-Plus MPSoC SOM implements single-Chip 10/100/1000 Mbps Ethernet Transceiver, with 1.8 V IO operating voltage using Gigabit ethernet PHY “KSZ9031RNX”. It provides the Reduced Gigabit Media Independent Interface (RGMII) and is connected to the Gigabit Ethernet controller of PS MIO bank 502.

EagleCore ZU-Plus MPSoC SOM support high speed USB 2.0 On-The-Go (OTG) transceiver with 24 MHz operating frequency. The board uses “USB3340” ULPI transceiver and supports both device and host modes. It is connected to the OTG controller of PS MIO bank and works at 1.8V voltage.

Note: The OTG will operate in Host mode when jumper W2 is closed and will operate in Device mode when W2 is open. By default, it operates in Host mode. While working as a Host, the device connected to the FPGA can only draw current up to 300 mA.

EagleCore ZU-Plus MPSoC SOM features MAC ID EEPROM, which is a memory chip that stores the unique MAC address of a network interface. It is a non-volatile memory that interfaces with PS MIO Bank 501 of Zynq UltraScale+ MPSoC.  It operates at a voltage of 3.3 V.

The EagleCore ZU-Plus MPSoC features an in-built RTC functionality to maintain accurate time within the system. A 32.768 kHz crystal is connected to BANK 503 of the FPGA to support this functionality.

EagleCore ZU-Plus MPSoC SOM have UART interface connected to PS UART controller peripheral of the device in Bank 501. UART offer a flexible and user-friendly solution for incorporating serial communication interfaces, facilitating seamless data exchange with external devices across a diverse array of applications. It operates at a voltage of 3.3 V.

The CAN protocol is commonly utilized in FPGA-based systems for robust and reliable communication between various embedded devices and controllers. It will facilitate seamless data exchange and networking capabilities within their embedded applications. Eaglecore ZU-Plus MPSoC offers two CAN communication using CAN controller in PS MIO bank 501. Its operating voltage is 3.3V.

CAN0

CAN1 (Optional)

Note: CAN1 option is available upon customer request.

EagleCore ZU-Plus MPSoC has MIPI CSI-2 feature that can be incorporated in the carrier board. MIPI can be useful for high-quality image and video data transmission. It is connected to the bank 66 of HP in the PL section with the voltage 1.2V and MIPI controller signals are connected to HD bank. Hp bank works in the voltage of 1.2 V and HD in 3.3V.

Note: Bank 26/46, Bank 24/44: Bank 46 and 44 is supported for the part number XCZU3TCG and XCZU3TEG, while Bank 26 and 24 is supported for the part number XCZU3CG and XCZU3EG.

Note: Bank 24 is for the part numbers XCZU3CG and XCZU3EG. Bank 44 is for the part numbers XCZU3TCG and XCZU3TEG.

The EagleCore ZU-Plus MPSoC SOM offers user defined high speed transceiver lanes for custom application purposes. The user can make use of USB 3.0, SATA, PCIe and Display port functionality through 4 lanes of GTR lines in PS section. The board also supports 4 lanes of GTH lines in PL section.

PS GTR

PL GTH

Note: Bank 224 is only available for the part number XCZU3CG and XCZU3EG.

HP Banks

Note: Bank 65 is not available for the part numbers XCZU3TCG and XCZU3TEG.

HD Banks

Note: Bank 26, 25 and 24 is for the part numbers XCZU3CG and XCZU3EG. Bank 46, 45 and 44 is for the part numbers XCZU3TCG and XCZU3TEG.

PS MIO

Note: Bank 224 is compatible only for the part numbers XCZU3TCG and XCZU3TEG.

*NOTE: The Connector P4 is only available for XCZU3EG and XCZU3CG.

Workflow for the Zynq series is slightly different than Series-7 FPGAs. There is a tutorial on quickly getting up and running with EagleCore to accelerate the pace of development.

Link: https://docs.numato.com/kb/getting-started-zynq-on-styx-using-vivado-design-suite/

The EagleCore ZU-Plus MPSoC SOM is factory configured to be powered only from the carrier so make sure that you have a carrier that can power the board properly.

The bitstream can be generated for EagleCore in Vivado by following the steps below:

Step 1:  It is recommended to generate .bin file along with .bit file. Right-click on “Generate Bitstream” under the “Program and Debug” section of the Flow Navigator window and click “Bitstream Settings”.

Step 2: Select “-bin_file” option in the dialog window and click “Apply” and then “OK”.

Step 3: Finally click “Generate Bitstream”.

EagleCore ZU-Plus MPSoC SOM facilitates easy reprogramming of SRAM and onboard SPI flash through JTAG programmer like “Xilinx Platform cable USB”. Following steps illustrate how to program FPGA on EagleCore using JTAG.

Step 1: By using JTAG cable, connect Xilinx platform cable USB to the carrier of EagleCore and power it up.

Step 2: Open Vivado project and open the target by clicking on the “Open Target” in “Open Hardware Manager” in the “Program and Debug” section of the Flow Navigator window. Select “Auto Connect”.

Step 3: If the device is detected successfully, then select “Program Device” after right clicking on the target device “” as shown below.

Step 4: In the dialog window which opens up, Vivado automatically chooses the correct bitstream file if the design was synthesized, implemented and bitstream generated successfully. If needed, browse to the bitstream which needs to be programmed to FPGA. Finally, click “Program”.

Programming the QSPI Flash for the Zynq and ZynqMP series is slightly different than Series-7 FPGAs. There is a tutorial on how to boot Styx from QSPI (as well as SD Card). Follow the same steps for EagleCore module also.
Link: Styx: Boot from SD card and QSPI flash

*All parameters considered nominal. Numato Systems Pvt Ltd reserves the right to modify products without notice.

Vivado XDC Constraints

EagleCore ZU-Plus IO Length Details