Callisto Spartan 6 USB 3.1 FPGA Module

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Callisto S6 is an easy to use FPGA Development board featuring the Xilinx Spartan 6 FPGA with 2Gb DDR3 SDRAM. This board contains the Xilinx XC6SLX150– FGG676 FPGA. The high-speed USB 3.1 interface (USB-C connector) provides fast and easy configuration download to the onboard SPI flash. There is no need for a programmer or special downloader cable to download bitstream to the board. The Development board also provides easy access to JTAG signals on a standard Xilinx Platform Cable compatible header. Callisto S6 provides the user the flexibility of adding their own peripherals through IO Expansion Headers.

Features

  • FPGA: Spartan XC6SLX150 in FGG676 package
  • DDR3: 2Gb DDR3 (MT41J128M16HA-125:K or equivalent)
  • Flash memory: 128 Mb Quadbit SPI flash memory (N25Q128A13ESE40E)
  • 2 x 100MHz CMOS oscillator
  • USB 3.1 Gen1 @5Gbps (USB Type-C connector)
  • JTAG header for programming and debugging
  • 12V DC power supply
  • A Push Button for the reset pin
  • 284 IOs for user-defined purposes
  • Onboard voltage regulators for single power rail operation
Category:

Description

Callisto S6 is an easy to use FPGA Development board featuring the Xilinx Spartan 6 FPGA with 2Gb DDR3 SDRAM. This board contains the Xilinx XC6SLX150– FGG676 FPGA. The high-speed USB 3.1 interface (USB-C connector) provides fast and easy configuration download to the onboard SPI flash. There is no need for a programmer or special downloader cable to download bitstream to the board. The Development board also provides easy access to JTAG signals on a standard Xilinx Platform Cable compatible header. Callisto S6 provides the user the flexibility of adding their own peripherals through IO Expansion Headers.
Features

  • FPGA: Spartan XC6SLX150 in FGG676 package
  • DDR3: 2Gb DDR3 (MT41J128M16HA-125:K or equivalent)
  • Flash memory: 128 Mb Quadbit SPI flash memory (N25Q128A13ESE40E)
  • 2 x 100MHz CMOS oscillator
  • USB 3.1 Gen1 @5Gbps (USB Type-C connector)
  • JTAG header for programming and debugging
  • 12V DC power supply
  • A Push Button for the reset pin
  • 284 IOs for user-defined purposes
  • Onboard voltage regulators for single power rail operation

Applications

  • Signal Processing
  • Product Prototype Development
  • Communication devices development
  • Educational tool for Schools and Universities
  • Development and testing of custom embedded processors
  • Accelerated Computing Integration

Additional information

FPGA

Memory

Number Of GPIOs (Max)

284

Configuration Options

JTAG

Non-Volatile Configuration Storage

N25Q128A13ESE40E

Number of Clock Sources

2

Communication

USB 3.1

Primary Clock Frequency

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