Introduction
Styx SODIMM incorporates the AMD Zynq XC7Z020 chip, which seamlessly integrates programmable logic with a dual-core ARM Cortex-A9 processor. This integration provides a potent blend of hardware and software processing capabilities, all within a single chip. Zynq series feature a hard System on Chip (SoC) with an ARM core and the range of peripherals offered includes an extensive array of functionalities, such as UARTs, Ethernet controllers, USB ports, timers, interrupt controllers, and various other features. It has a seamless integration of the Processing System(PS) with the Programmable Logic (PL) in which the interaction between them is enabled by a high-bandwidth interface, ensuring communication and efficient data transfer between them. Styx SODIMM is specifically designed for the development and integration of FPGA based accelerated features into other larger designs. It opens up a vast realm of possibilities for implementing innovative solutions across a wide range of applications.
Board Features
- Device: XC7Z020 in CLG484 package, Speed Grade: -1
- DDR3: 4Gb DDR3L (MT41K256M16TW-107 IT:P TR or equivalent)
- Flash memory: 128 Mb Quad bit SPI flash memory (N25Q128A13EF840E)
- 33 MHz CMOS oscillator
- 100 MHz CMOS oscillator
- Gigabit Ethernet, Real Time Clock, Trusted Platform Module
- High-Speed USB 2.0 OTG interface.
- Flash programming via JTAG and USB
- Micro SD card slot for memory expansion
Applications
- Product Prototype Development
- Accelerated computing integration
- Custom Embedded platform
- Signal Processing
- Communication devices development
- Educational tool for Schools and Universities
Reference clock
Bank | Pin No. | Signal Name | Function |
---|---|---|---|
500 | F7 | PS_CLK_500 | 33.33 MHz CLK |
34 | B19 | IO_L13P_T2_MRCC_35 | 100 MHz CLK |
DDR3L SDRAM
Styx SODIMM includes DDR3L memory technology which is the third generation of DDR memory technology designed to operate at lower voltage levels (1.35 V) compared to standard DDR3 modules. Styx SODIMM uses two micron MT41K256M16TW-107 IT:P TR memory, has a capacity of 256 megabits (Mbits) organized into 16 million addresses., totaling 1 GB of RAM. DDR3L is connected to PS section of Zynq-7000 AP SoC and has the speed up to 1866 MT/s.
QSPI Flash
The Styx SODIMM has 128 Mb of Quad bit SPI flash memory. It is serial NOR flash which operates at the voltage of 3.3 V. SPI flash connects to the Zynq PS QSPI interface and serves as the Zynq SoC’s default boot device. QSPI flash memory can be increased to 8GB using eMMC flash (optional).
Bank | Pin No. | Signal Name | Function |
---|---|---|---|
500 | A1 | PS_MIO1_500 | SPI_CS_N |
500 | A2 | PS_MIO2_500 | SPI_DQ[0] |
500 | F6 | PS_MIO3_500 | SPI_DQ[1] |
500 | E4 | PS_MIO4_500 | SPI_DQ[2] |
500 | A3 | PS_MIO5_500 | SPI_DQ[3] |
500 | A4 | PS_MIO6_500 | SPI_SCK |
Micro SD Card
The Styx SODIMM incorporates two micro-SD card slots, with one located in the SODIMM itself (SD) and the other on the carrier board (SD0). SD0 can be used to store non-volatile external memory as well as to boot the Zynq-7000 AP SoC. Both the slots are connected to the PS MIO banks and eMMC flash can be multiplexed with SD pins.
Bank | Pin No. | Signal Name | Function |
---|---|---|---|
500 | G7 | PS_MIO10_500 | SD_DAT3 |
500 | B4 | PS_MIO11_500 | SD_DAT2 |
500 | C5 | PS_MIO12_500 | SD_DAT1 |
500 | A6 | PS_MIO13_500 | SD_DAT0 |
500 | B6 | PS_MIO14_500 | SD_CMD |
500 | E6 | PS_MIO15_500 | SD_CLK |
Bank | Pin No. | Signal Name | Function |
---|---|---|---|
501 | E14 | PS_MIO40_501 | SD0_CLK |
501 | C8 | PS_MIO41_501 | SD0_CMD |
501 | D8 | PS_MIO42_501 | SD0_DAT0 |
501 | B11 | PS_MIO43_501 | SD0_DAT1 |
501 | E13 | PS_MIO44_501 | SD0_DAT2 |
501 | B9 | PS_MIO45_501 | SD0_DAT3 |
eMMC Flash
Styx SODIMM supports eMMC Flash and is multiplexed with micro-SD card slot pins in SODIMM. It can be used as additional storage for SPI flash and as a secondary boot device. It operates at a voltage level of 3.3 V and supports up to 4 bit mode.
Ethernet
Styx SODIMM implements single-Chip 10/100/1000 Mbps Ethernet Transceiver, with 1.8 V operating voltage. It provides the Reduced Gigabit Media Independent Interface (RGMII) and is connected to the PS MIO bank in Zynq-7000 AP SOC.
Bank | Pin No. | Signal Name | Function |
---|---|---|---|
501 | D6 | PS_MIO16_501 | ETH_TXCLK |
501 | E9 | PS_MIO17_501 | ETH_TXD0 |
501 | A7 | PS_MIO18_501 | ETH_TXD1 |
501 | E10 | PS_MIO19_501 | ETH_TXD2 |
501 | A8 | PS_MIO20_501 | ETH_TXD3 |
501 | F11 | PS_MIO21_501 | ETH_TXCTL |
501 | A14 | PS_MIO22_501 | ETH_RXCLK |
501 | E11 | PS_MIO23_501 | ETH_RXD0 |
501 | B7 | PS_MIO24_501 | ETH_RXD1 |
501 | F12 | PS_MIO25_501 | ETH_RXD2 |
501 | A13 | PS_MIO26_501 | ETH_RXD3 |
501 | D7 | PS_MIO27_501 | ETH_RXCTL |
501 | D10 | PS_MIO52_501 | ETH_MDC |
501 | C12 | PS_MIO53_501 | ETH_MDIO |
USB 2.0 OTG
Styx SODIMM support high speed USB 2.0 On-The-Go (OTG) transceiver in 24 MHz operating frequency. OTG technology supports both device and host modes. The ULPI (UTMI+ Low Pin Interface) protocol is utilized to establish a connection between MIO (Multi-Function Input/Output) pins and the PHY (Physical Layer) component.
Bank | Pin No. | Signal Name | Function |
---|---|---|---|
501 | A12 | PS_MIO28_501 | USB_D4 |
501 | E8 | PS_MIO29_501 | USB_DIR |
501 | A11 | PS_MIO30_501 | USB_STP |
501 | F9 | PS_MIO31_501 | USB_NXT |
501 | C7 | PS_MIO32_501 | USB_D0 |
501 | G13 | PS_MIO33_501 | USB_D1 |
501 | B12 | PS_MIO34_501 | USB_D2 |
501 | F14 | PS_MIO35_501 | USB_D3 |
501 | A9 | PS_MIO36_501 | USB_CLK |
501 | B14 | PS_MIO37_501 | USB_D5 |
501 | F13 | PS_MIO38_501 | USB_D6 |
501 | C13 | PS_MIO39_501 | USB_D7 |
Trusted Platform Module
The Trusted Platform Module(TPM) is an integrated security module for hardware authentication. The security module is used primarily for cryptographic key generation, key storage and key management as well as generation and secure storage for digital certificates.
Bank | Pin No. | Signal Name | Function |
---|---|---|---|
33 | W16 | IO_L14P_T2_SRCC_33 | TPM_CLK |
33 | Y16 | IO_L14N_T2_SRCC_33 | TPM_CS |
33 | U15 | IO_L15P_T2_DQS_33 | TPM_RST |
33 | U16 | IO_L15N_T2_DQS_33 | TPM_MISO |
33 | U17 | IO_L16P_T2_33 | TPM_MOSI |
Real Time Clock
Styx SODIMM includes Real Time Clock (RTC), an integral part of electronic devices that operates independently of the device to accurately track real-world time. It is connected to PL IO pins and has an operating voltage of 3.3 V.
Bank | Pin No. | Signal Name | Function |
---|---|---|---|
34 | M19 | IO_L13P_T2_MRCC_34 | RT_SCL |
34 | M20 | IO_L13N_T2_MRCC_34 | RT_SDA |
MAC EEPROM
Styx SODIMM features MAC ID EEPROM, which is a memory chip that stores the unique MAC address of a network interface. It is a non-volatile memory that interfaces with PS of Zynq-7000 AP SoC. It operates at a voltage of 1.8 V.
Bank | Pin No. | Signal Name | Function |
---|---|---|---|
501 | D11 | PS_MIO48_501 | MAC_SCL |
501 | C14 | PS_MIO49_501 | MAC_SDA |
UART
Styx SODIMM have UART interface connected to PS UART peripheral of the device. UART offer a flexible and user-friendly solution for incorporating serial communication interfaces, facilitating seamless data exchange with external devices across a diverse array of applications.
Bank | Pin No. | Signal Name | Function |
---|---|---|---|
501 | D13 | PS_MIO50_501 | UART_RX |
501 | C10 | PS_MIO51_501 | UART_TX |
I2C
Styx SODIMM offers I2C communication through PS I2C peripheral and offers a flexible and efficient solution for establishing communication with various peripheral devices using the I2C protocol. It has a operating voltage of 1.8 V.
Bank | Pin No. | Signal Name | Function |
---|---|---|---|
501 | D12 | PS_MIO46_501 | I2C_SCL |
501 | B10 | PS_MIO47_501 | I2C_SDA |
CAN
Styx SODIMM includes a second generation high-speed CAN transceiver with an operating voltage of 3.3 V. It has a data rate of 8 Mbps in normal mode and is linked to PS MIO of Zynq-7000 AP SoC.
Bank | Pin No. | Signal Name | Function |
---|---|---|---|
500 | E5 | PS_MIO8_500 | CAN_RXD |
500 | G4 | PS_MIO9_500 | CAN_TXD |
Programming QSPI Flash
Programming the QSPI Flash for the Zynq series is slightly different than Series-7 FPGAs. There is a tutorial on how to flash and boot Styx from QSPI (as well as SD Card).
Link: Styx: Boot from SD card and QSPI flash
eMMC can be used as additional storage space for QSPI. It can provide up to 8GB of additional memory. The QSPI flash serves as the primary boot device, while the SD card and eMMC function as secondary boot devices.
Petalinux
PetaLinux is an open-source Linux operating system that offers a simplified process for configuring, constructing, and customizing Linux distributions to meet the specific needs of Zynq-7000 devices. PetaLinux provides an extensive collection of device drivers, granting convenient access to a wide array of peripherals and interfaces present on Zynq-7000 devices. These peripherals encompass UARTs, Ethernet controllers, USB ports, I2C, SPI, and numerous others, empowering developers to utilize the complete range of functionalities offered by the Zynq-7000 platform.
Styx SODIMM can be utilized for creating Petalinux based FPGA projects. You can find a demonstration of a HelloWorld project created using PetaLinux by following the link provided here.
Technical Specifications
Parameter * | Value | Unit |
---|---|---|
Basic Specifications | ||
Number of GPIOs | 150 + 8 (Max) | |
On-board oscillator frequency | 33.33 | MHz |
On-board oscillator frequency (ASEM1-100.000MHZ-LC-T) | 100 | MHz |
DDR3 Capacity | 1 | GB |
Quad SPI Flash Memory (N25Q128A13ESE40E) | 128 | Mb |
Power supply voltage (External) | 5 - 12 | V |
Programmable Logic Specifications | ||
Internal supply voltage relative to GND | -0.5 to 1.1 | V |
Auxiliary supply voltage relative to GND | -0.5 to 2.0 | V |
Output drivers supply voltage relative to GND | -0.5 to 3.6 | V |
Processing Section Specifications | ||
PS MIO I/O supply voltage (VCCO_MIO) | -0.5 to 3.6 | V |
PS MIO I/O input voltage | -0.40 to VCCO_MIO + 0.55 | V |
PS DDR I/O input voltage | -0.55 to VCCO_DDR + 0.55 | V |
Maximum Processor Frequency | 667 | MHz |
* All parameters considered nominal. Numato Systems Pvt Ltd reserves the right to modify products without notice.
SODIMM PCB Edge Connector Pinout Map
Signal | SODIMM Pin (Top) | SODIMM Pin (Bottom) | Signal |
---|---|---|---|
GND | 1 | 2 | GPHY_ATXRX_N |
NC | 3 | 4 | GPHY_ATXRX_P |
GND | 5 | 6 | GPHY_BTXRX_N |
PL_IO_L19N_T3_VREF_13 | 7 | 8 | GPHY_BTXRX_P |
PL_IO_L19P_T3_13 | 9 | 10 | P1_2 |
GPHY_LINK_LED2 | 11 | 12 | GPHY_ACTIVITY_LED1 |
GND | 13 | 14 | GPHY_CTXRX_N |
GPHY_DTXRX_N | 15 | 16 | GPHY_CTXRX_P |
GPHY_DTXRX_P | 17 | 18 | PL_IO_L11N_T1_SRCC_13 |
PL_IO_L11P_T1_SRCC_13 | 19 | 20 | VIN_3V3 |
PL_IO_L22P_T3_13 | 21 | 22 | PL_IO_L15P_T2_DQS_13 |
PL_IO_L22N_T3_13 | 23 | 24 | PL_IO_L15N_T2_DQS_13 |
NC | 25 | 26 | PL_IO_L12P_T1_MRCC_13 |
GND | 27 | 28 | PL_IO_L12N_T1_MRCC_13 |
PL_IO_L20P_T3_13 | 29 | 30 | PL_IO_18P_T2_13 |
PL_IO_L20N_T3_13 | 31 | 32 | VIN_3V3 |
PL_IO_L18N_T2_13 | 33 | 34 | PL_IO_L1N_T0_34 |
PL_IO_L2N_T0_34 | 35 | 36 | PL_IO_L1P_T0_34 |
PL_IO_L2P_T0_34 | 37 | 38 | PL_IO_L10N_T1_34 |
PL_IO_L10P_T1_34 | 39 | 40 | GND |
GND | 41 | 42 | PL_IO_L18N_T2_34 |
PL_IO_L23N_T3_34 | 43 | 44 | PL_IO_L18P_T2_34 |
PL_IO_L23P_T3_34 | 45 | 46 | VIN_3V3 |
P2_2 | 47 | 48 | PL_IO_L17N_T2_13 |
NC | 49 | 50 | PL_IO_L17P_T2_13 |
GND | 51 | 52 | PL_IO_L13N_T2_MRCC_13 |
PL_IO_L14N_T2_SRCC_13 | 53 | 54 | PL_IO_L13P_T2_MRCC_13 |
PL_IO_L14P_T2_SRCC_13 | 55 | 56 | PL_IO_L21N_T3_DQS_13 |
PL_IO_L16N_T2_13 | 57 | 58 | PL_IO_L21P_T3_DQS_13 |
PL_IO_L16P_T2_13 | 59 | 60 | VIN_3V3 |
PL_IO_L8N_T1_34 | 61 | 62 | PL_IO_L4N_T0_34 |
PL_IO_L8P_T1_34 | 63 | 64 | PL_IO_L4P_T0_34 |
GND | 65 | 66 | PL_IO_L7N_T1_34 |
PL_IO_L11N_T1_SRCC_34 | 67 | 68 | PL_IO_L7P_T1_34 |
PL_IO_L11P_T1_SRCC_34 | 69 | 70 | PL_IO_L17P_T2_34 |
PL_IO_L6N_T0_VREF_34 | 71 | 72 | VIN_3V3 |
PL_IO_L6P_T0_34 | 73 | 74 | PL_IO_L17N_T2_34 |
P1_7 | 75 | 76 | P2_5 |
USB_OTG_ID | 77 | 78 | USB_PWR_EN |
GND | 79 | 80 | PL_IO_L3P_T0_DQS_PUDC_B_34 |
USB_OTG_DP | 81 | 82 | NC |
USB_OTG_DM | 83 | 84 | NC |
NC | 85 | 86 | PL_IO_L9P_T1_DQS_34 |
NC | 87 | 88 | VIN_3V3 |
PL_IO_L9N_T1_DQS_34 | 89 | 90 | PL_IO_L12P_T1_MRCC_34 |
P2_1 | 91 | 92 | PL_IO_L12N_T1_MRCC_34 |
P1_4 | 93 | 94 | PL_IO_L22P_T3_34 |
GND | 95 | 96 | PL_IO_L22N_T3_34 |
PL_IO_L5P_T0_34 | 97 | 98 | PL_IO_L21P_T3_DQS_34 |
PL_IO_L5N_T0_34 | 99 | 100 | PL_IO_L21N_T3_DQS_34 |
PL_IO_L20P_T3_34 | 101 | 102 | PL_IO_L16P_T2_34 |
PL_IO_L20N_T3_34 | 103 | 104 | PL_IO_L16N_T2_34 |
GPIO48_PS_MIO48_501 | 105 | 106 | VIN_3V3 |
SD0_DATA0(PS_MIO42_501) | 107 | 108 | SD0_CMD(PS_MIO41_501) |
SD0_CLK(PS_MIO40_501) | 109 | 110 | P2_6 |
SD0_DATA1(PS_MIO43_501) | 111 | 112 | SD0_DATA2(PS_MIO44_501) |
GND | 113 | 114 | SD0_DATA3(PS_MIO45_501) |
I2C0_SDA(PS_MIO47_501) | 115 | 116 | I2C0_SCL(PS_MIO46_501) |
UART0_RX(PS_MIO50_501) | 117 | 118 | UART0_TX(PS_MIO51_501) |
PL_IO_L14N_T2_SRCC_34 | 119 | 120 | PL_IO_L15N_T2_DQS_34 |
PL_IO_L14P_T2_SRCC_34 | 121 | 122 | PL_IO_L15P_T2_DQS_34 |
P1_8 | 123 | 124 | VIN_3V3 |
PL_IO_L23P_T3_35 | 125 | 126 | PL_IO_L21P_T3_DQS_AD14P_35 |
NC | 127 | 128 | NC |
NC | 129 | 130 | NC |
GND | 131 | 132 | PL_IO_L22N_T3_AD7N_35 |
PL_IO_L23N_T3_35 | 133 | 134 | PL_IO_L20P_T3_AD6P_35 |
NC | 135 | 136 | PL_IO_L12P_T1_MRCC_35 |
NC | 137 | 138 | PL_IO_L22P_T3_AD7P_35 |
PL_IO_L24P_T3_AD15P_35 | 139 | 140 | P2_8 |
NC | 141 | 142 | VIN_3V3 |
PL_IO_L8N_T1_AD10N_35 | 143 | 144 | P2_7 |
PL_IO_L8P_T1_AD10P_35 | 145 | 146 | PL_IO_L7P_T1_AD2P_35 |
PL_IO_L7N_T1_AD2N_35 | 147 | 148 | PL_IO_L9P_T1_DQS_AD3P_35 |
PL_IO_L9N_T1_DQS_AD3N_35 | 149 | 150 | PL_IO_L11P_T1_SRCC_35 |
GND | 151 | 152 | PL_IO_L14P_T2_AD4P_SRCC_35 |
PL_IO_L10N_T1_AD11N_35 | 153 | 154 | PL_IO_L10P_T1_AD11P_35 |
P1_3 | 155 | 156 | P2_3 |
PL_IO_25_35 | 157 | 158 | PL_IO_L12N_T1_MRCC_35 |
PL_IO_L14N_T2_AD4N_SRCC_35 | 159 | 160 | VIN_3V3 |
P1_1 | 161 | 162 | PL_IO_L17P_T2_AD5P_35 |
PL_IO_L24N_T3_AD15N_35 | 163 | 164 | PL_IO_L17N_T2_AD5N_35 |
PL_IO_L18N_T2_AD13N_35 | 165 | 166 | PL_IO_L20N_T3_AD6N_35 |
P1_5 | 167 | 168 | P2_4 |
GND | 169 | 170 | PL_IO_L15P_T2_DQS_AD12P_35 |
PL_IO_L18P_T2_AD13P_35 | 171 | 172 | PL_IO_L15N_T2_DQS_AD12N_35 |
P1_6 | 173 | 174 | PL_IO_L1P_T0_AD0P_35 |
PL_IO_L5P_T0_AD9P_35 | 175 | 176 | PL_IO_L4P_T0_35 |
PL_IO_L3N_T0_DQS_AD1N_35 | 177 | 178 | PL_IO_L4N_T0_35 |
PL_IO_L5N_T0_AD9N_35 | 179 | 180 | VIN_3V3 |
PL_IO_L3P_T0_DQS_AD1P_35 | 181 | 182 | NC |
VRTC | 183 | 184 | NC |
GND | 185 | 186 | GND |
n_RST_IN | 187 | 188 | NC |
PL_IO_L1N_T0_AD0N_35 | 189 | 190 | PL_IO_L2N_T0_AD8N_35 |
JTAG_TDO | 191 | 192 | VIN_3V3 |
NC | 193 | 194 | PL_IO_0_35 |
JTAG_TDI | 195 | 196 | PL_IO_L2P_T0_AD8P_35 |
JTAG_TCK | 197 | 198 | GND |
JTAG_TMS | 199 | 200 | VBUS1 |